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There are two points about your question.
- Altera "hot-socketing-feature" allows to power-up supply rails in any sequence.
- Altera suggests a specific sequence (1.1V core voltage before 2.5 and 3V) for minimal current transients. Otherwise your power supply must be prepared for larger inrush currents. Review Cyclone V handbook chapter 10 Power Management for details.
I didn't yet care for power sequence in cyclone V designs but observed no problems with excessive inrush currents. So I suggest to try first with the simple circuit.
Deriving the 1.1V core voltage from 3.3V supply is quite common for smaller system that don't have huge core current demand.
Checking a number of development kit schematics and the custom designs I was working with, I notice that they all supply the core voltage regulator from primary 5 or 12 V input, so they can power the 1.1V independently (and before the other FPGA voltages if necessary). But there are no specific means to delay one against the other voltage, e.g. different soft start capacitor values. I still think that they would work with 2.5 to 3.3V before 1.1V.
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