Hugo17
Junior Member level 1
I do have following block diagram which I would like to connect with a bus that use a generic parameter (adc). The blockdiagram looks like this:
The implementation for the file "block_name.vhd" is:
Does someone know how to fix this problem?
Thanks!
The implementation for the file "block_name.vhd" is:
Code:
LIBRARY ieee;
USE ieee.std_logic_1164.all;
-- Entity Declaration
ENTITY block_name IS
-- {{ALTERA_IO_BEGIN}} DO NOT REMOVE THIS LINE!
GENERIC(width : INTEGER := adc);
PORT
(
gi_bus : OUT STD_LOGIC_VECTOR(width to 0)
);
-- {{ALTERA_IO_END}} DO NOT REMOVE THIS LINE!
END block_name;
-- Architecture Body
ARCHITECTURE block_name_architecture OF block_name IS
BEGIN
END block_name_architecture;
Does someone know how to fix this problem?
Thanks!