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Have you decided on your Master and Slave modules?
The AHB bus would provide data to be transferred between b/w the M and S. Without a Master and Slave an AHB i/f would be meaningless.
Download the AHB Lite spec from ARM and read it too.
oh, btw - Have you solved the problem of your thread - What am I do if I have to take 4KB+a address in AXI Bus?
I see that it was posted today. Now I see you have jumped to AXI!
Advice - Stick to one protocol at a time until u completely understand it.
Have you decided on your Master and Slave modules?
The AHB bus would provide data to be transferred between b/w the M and S. Without a Master and Slave an AHB i/f would be meaningless.
Download the AHB Lite spec from ARM and read it too.
oh, btw - Have you solved the problem of your thread - What am I do if I have to take 4KB+a address in AXI Bus?
I see that it was posted today. Now I see you have jumped to AXI!
Advice - Stick to one protocol at a time until u completely understand it.
Firstly Thanks for letting me with answer,
Yes, 3 Maser Module + 5 Slave + Peripheral(ARM's i2c, uart, GPIO, ... )
This architecture are consisted with low BandWidth modules. it means that it does not matter about B/W.
Specifically, it needs to multiple master so i think that it makes by using AHB Lite.
(I don't know AHB-Lite Throughput B/W Limit)
But in this case, it will be much better choice.
AHB lite is single master protocol. Full AHB is multi master protocol. However, you can use AHB Bus matrix to arbitrate and multiplex AHB master before connecting it to AHB lite bus.
AHB lite is single master protocol. Full AHB is multi master protocol. However, you can use AHB Bus matrix to arbitrate and multiplex AHB master before connecting it to AHB lite bus.
If you want single master + multi-slave you can go for AHB-Lite.
For Multi-Master + Multi-slave go for normal AHB.
For your case it seems AHB will suffice.
If you want single master + multi-slave you can go for AHB-Lite.
For Multi-Master + Multi-slave go for normal AHB.
For your case it seems AHB will suffice.
See..........now you are deviating on what you has asked in #1. Not good!
Mark this thread solved/closed and start a new one, if you want to base your AHB Lite question *keeping in mind that it has to be connected to a Cortex M0*.
On a side note - please understand the architecture before framing a question.
See..........now you are deviating on what you has asked in #1. Not good!
Mark this thread solved/closed and start a new one, if you want to base your AHB Lite question *keeping in mind that it has to be connected to a Cortex M0*.
On a side note - please understand the architecture before framing a question.
You have changed/updated your original Q by adding more info over its course.
So you have to mention specifically for which updated Q, you would like an answer!
But as this marked as solved so I won't bother anymore.
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