zoom8848
Newbie level 4
Could PLL successfully lock a signal which is not 50%duty cycle?
I‘m learning Analog integerated circuit. Just readed the PLL chapter.
Since a PLL can perfect trace the phase and frequency of input signal, whatif it's a signal with perfect periodicity but do not have a 50% duty cycle(let's say 30%), will the PLL successfully lock and trace the input ?
I‘m learning Analog integerated circuit. Just readed the PLL chapter.
Since a PLL can perfect trace the phase and frequency of input signal, whatif it's a signal with perfect periodicity but do not have a 50% duty cycle(let's say 30%), will the PLL successfully lock and trace the input ?
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