Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] [moved] HELP Testbench VGA CORE for AGC 10gbps

Status
Not open for further replies.

Andriy7

Newbie level 3
Joined
Jan 19, 2016
Messages
3
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
30
Hello everybody!!
This is my first post, I have 2 years in microelectronics RFIC area. I am trying to design an AGC for optical receiver 10Gbps. I read a lot of papers and I know the blocks necessary to build it now I am in the VGA block but my principal problem is the testbench in cadence.

I am trying to measure S21 of VGA, but the result of simulation is very bizarre so I am sure that my problem is in the testbench.

I used this circuit before like FT doubler(Vin+ Vbias Vin-) and it works perfect, now to convert this into VGA I read that the difference is in the connections of the input Vin+ Vin- Vin+, but I have S21 like -300dB.

Please I want to know what I am doing wrong. Thanks a lot!.

Best Regards!

The balun is single ended=50, differential output=100
gilbert cell.pnggilbert cell zoom.pnggilbert cell results.png
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top