Process Variation Control for Subthreshold Devices

I'm working on a circuit that has two subthreshold diode connected transistors. I believe these two devices have the most impact on the variation in the circuit (with a Monte Carlo Analysis). I think it would be due to the exponential dependence on threshold voltage in the subthreshold region. I've managed to reduce the effects of process variation everywhere else in the circuit, but I cannot think of a way to reduce the variation in the subthreshold portion of the circuit. Gate area is maximized in accordance to Pelgrom's Law, and I cannot use adaptive body biasing as this is a fully depleted SOI process.
This is my first time working with subthreshold devices as well as process/mismatch sensitive devices, any tips on design methodology would be greatly appreciated.

Which technology and what kind of circuit is it?

Hello,


The circuit is a bandgap reference, very similar to the Banba reference (replace the BJT diodes with mosfets), the technology is a FinFET process, unfortunately I cannot say much more about the process. The idea behind the circuit is to use the subthreshold devices in a way that mimics the behaviour of the BJT.

I know that the OP Amp has a significant effect on the reference voltage, but one thing I noticed was that the voltage across the diodes had the most significant variation when subjected to process variations. Mismatch does not have much, if any, of an effect on my circuit, which is why I did not think it was the amplifier. The strong dependence on threshold voltage in subthreshold operation would dictate the variations of voltage across the diodes which is why I am trying to come up with a way to reduce that, either by sizing(which I have done, W*L is large), or by implementing some feedback.


Thanks!

ljp2706 said:

... I think it would be due to the exponential dependence on threshold voltage in the subthreshold region.

Click to expand...

Can't you provide constant current to the diode connected transistors? Temperature dependency of Vds=Vgs is very low.

So the voltage drop across the diode would be a function of how much current is flowing through it? If I bias the current mirrors in a way such that the maximum current it can supply is equal to the worst case, then it would be constant for both corners?

Would source degeneration on the current mirror help with process variations at all?

Ok. But You see a problem in reference voltage peak-to-peak variation across temperature or only reference value across corners?
If second case, I'm not sure if You are able to overcame it without trimming - opamp replicate one VGS to other with the same threshold variation (which from ff to ss could be quite high and independent to designer), so reference variation across corners should be proportional to threshold variations.

FDSOI technologies allowing body biasing to control threshold in general…

The only thing which comes quickly to my head is to use longer fets for which SS should be smaller (e.g. not 90 but 70 mV/dec)

BTW. Without any quantitative results it is hard to say more…

My temperature coefficient is fine, it is the second case unfortunately. I was informed that in the FinFET technology, the body effect parameter is practically 0 and my efforts in creating a bias network capable of adjusting threshold voltage proved it doesn't work. Do you think it would be feasible to create a process sensing DAC because I would really like to further reduce the variation without the use of trimming.

Also, is there anything else I can do to the diodes?

Right now I just have one diode in each branch, would making a diode stack, self-cascoding, or putting them in parallel help at all?

You can use Vth monitor and smart feedback to control sthing in the circuit but I don't have a solution close at hand now. But I remember that guys from Rio Grande(?) University working on mosfets only PVT insensitive references for last few years.

Check (on google scholar or ieeexplore) papers published by Hamilton Klimach and his team.

So after writing what I did, I realized my diodes should be more than a single diode...I replaced it with 3 parallel instances and the variation reduced by a factor of 4.4. Worst case PPM of an individual reference is around 50PPM, is this acceptable by general standards?

I actually hadn't heard of that research before, thanks for letting me know I'll take a look at that!

Oh, by the way, would anyone happen to know how to perform a DC temperature sweep after completing a transient simulation? I incorporated feedback that requires an initial few nanoseconds of convergence in order to properly work. Right now I have been using the dynamic parameter option in the transient simulation to adjust temperature, but I feel like there must be a way to start a DC simulation with the transient operating point at 100ns...

I am using Cadence 6.16