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Well I'm not very proficient in Verilog so maybe that's why I'm thinking it's so hard and can't really understand the circuit. Also can I do this all in one module or should I make multiple modules and then connect them all
You are lucky, in general it's not so often to have a diagram so deeply detailed. Yes, the standard approach to have a code easy to debug piece by piece, is you create and test separate modules and gradually connect them once approved in tests. Anyway, would help more if you understand exactly what is said in the textbook from where this drawing was extracted.
I don't have the book yet, my teacher just gave it to us and went over it briefly tried to get help from him but not available. So just trying to understand it.
What is missing from the drawing is any concept of a clock and pipe-lining. As drawn, if directly translated to Verilog it would end up being a big slow combinational circuit.
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