exp
Full Member level 1
Hi,
I am working in a 28nm process with 1V supply where I need gain and bandwidth. It's not really possible to use cascodes and not fun at all to even use a diff pair because gmro is effectively halfed: first lower VDS due to tail current source and second gain is gm*(ron//rop).
Now if I look at this years ISSCC so many designs use just inverters. Life would be fun with that: It's effectively self-biased, I get (gmn+gmp)/(gdn+gdsp), i.e. the full gmro and I don't need to waste precious headroom.
Inverters work fine in my design. However, CMRR=1. How do I really evaluate if I need CMRR>1 ? Why do all the ISSCC papers get away with CMRR=1?
Second, do I understand right that PSRR is independent of the tail current source? i.e. it does not matter if I have a diff pair or an inverter?
Since PSSR=Adm/Avdd where Avdd = vo/vdd, this results in a simple voltage divider. If I assume gdsn~gdsp, then Avdd~1/2 and hence PSSR=2*(gmn+gmp)/(gdsn+gdsp)=2*Adm. In this process even with an inverter I cannot expect more than Adm=5 which means PSRR=20dB. Is this a reasonable assumption, e.g. for an RF receiver IC?
I am working in a 28nm process with 1V supply where I need gain and bandwidth. It's not really possible to use cascodes and not fun at all to even use a diff pair because gmro is effectively halfed: first lower VDS due to tail current source and second gain is gm*(ron//rop).
Now if I look at this years ISSCC so many designs use just inverters. Life would be fun with that: It's effectively self-biased, I get (gmn+gmp)/(gdn+gdsp), i.e. the full gmro and I don't need to waste precious headroom.
Inverters work fine in my design. However, CMRR=1. How do I really evaluate if I need CMRR>1 ? Why do all the ISSCC papers get away with CMRR=1?
Second, do I understand right that PSRR is independent of the tail current source? i.e. it does not matter if I have a diff pair or an inverter?
Since PSSR=Adm/Avdd where Avdd = vo/vdd, this results in a simple voltage divider. If I assume gdsn~gdsp, then Avdd~1/2 and hence PSSR=2*(gmn+gmp)/(gdsn+gdsp)=2*Adm. In this process even with an inverter I cannot expect more than Adm=5 which means PSRR=20dB. Is this a reasonable assumption, e.g. for an RF receiver IC?
