how to proving the clocking block in systemverilog with ncverilog and simvision?

Code Verilog - [expand]
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module top();
    logic clk;
    initial begin
    clk =0;
    forever #5 clk= ~clk;
    end
    itf u_itf(.clk(clk));
    dut u_dut(u_itf);
    tb_u_tb(u_itf);
 
initial begin
$shm_open("./shm");
$shm_probe(top,"AS");
end
 
endmodule
 
    module tb (itf tb);
    initial begin
    tb.read <= 0;
    repeat(3) #10 tb.read <= ~tb.read;
    $finish;
    end
 
    always @(posedge tb.clk) begin
    tb.cb.read <=tb.cb;
    if (tb.cb.enable)
    tb.data  <= tb.data+1;
    end
 
    initial begin 
    tb.data =0;
    end
 
    endmodule
 
    module dut(itf dut_itf);
    always  @(posedge dut_itf.clk) begin
    if (dut_itf.read)
    dut_itf.enable <= 1;
    end
 
    initial begin 
    dut_itf.enable <= 0;
    end
    endmodule
 
    interface itf(input clk);
    logic read,enable;
    logic [7:0]  addr, data;
    modport dut(input read, addr, output data, enable);
    modport tb(clocking cb);
    
    clocking cb@(posedge clk);
    default input #3ns //output #5ns; //Here is my test point.
    output data, addr, read;
    input enable;
    endclocking
 
    endinterface