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what is the advantage of using 'logic' in systemverilog?

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u24c02

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Dear all,

I ran across the systemverilog data type of 'logic' in the internet.
But I'm verilog user so systemverilog does not familiar with this.
So does anyone know the reasone that why we have to use logic instead reg of verilog data type?

What is the difference between them?
 
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