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[SOLVED] Paralleling CMOS inverters (NOT logic gates)

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kathmandu

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Hello,

I need to use a CMOS gate (NOT) to invert the output signal of an optocoupler. Actually, one single inverter gate could be enough (the output current requirement is low) but I'll use a 74ACT14 chip which contains six inverters.

Is there any problem (signal transition glitches or something) if I'll put all of them in parallel?

(as a benefit, I thought It might further reduce the rise/fall times)
 

They are often paralleled to increase the current drive capacity; they are also often connected in series to introduce some delays (of the order of several ns).

How it is going to reduce rise/ fall times? I am not so sure.
 

By using six of them in parallel, the individual (capacitive) load is reduced thus the rise/fall transitions are enhanced. (am I wrong?)

I was afraid that having schmitt trigger inputs, every single inverter would switch the output at different input thresholds thus this might lead to transition glitches.

What do you think about this issue?
 

Hi,

There are single gate logic devices.

Look for 74HC1G14 or other logic families. Often in five pin SOT23, or even smaller in SC70.

Fairchild names them NC7SZ14..in different families.

Klaus
 

Thanks, Klaus, but I already have these inverter ICs (they are cheap & fast, btw). I could simply use just one gate (inverter) and put the other inverter's inputs to GND.

I was just wondering if there could be any benefit (in terms of speed) if I parallel them all.
 

Hi

kathmandu said:
and put the other inverter's inputs to GND.
Click to expand...

I'd have tied them all to V+ so the outputs are low. Is there any reason to do as you say in tying inputs to GND?

I have no idea if there is any benefit speedwise in paralleling them, maybe you are right, in my ignorance I would have thought that IC internal design played a larger - if not the only - role in speed. Does parallelling two MOSFETS alter their rise, store and fall times at all? I'm thinking of gate capacitance with all this.
 

I was reading a Mosfet driver datasheet (TC4422A) and I saw that the rise/fall times depend on load capacity.

After all, an increased (output) current will charge the load capacitance faster thus we got smaller rise/fall times.
 

If you want to quickly charge and discharge an external capacitor then you need as much current as you can get so paralleling the inverters will help. But without an external capacitor each inverter has a certain stray capacitance and paralleling inverters makes no difference since the total of the inverters equals the total of the stray capacitance.

An inverters logic IC has a single chip inside so all of its inverters are identical and will switch at almost the same voltage.

A power Mosfet has such a very high gate capacitance because it is made with thousands of tiny Mosfets in parallel. But a Cmos logic IC input has only a single tiny Mosfet with a fairly low gate capacitance.
 

Hi,

I was just wondering if there could be any benefit (in terms of speed) if I parallel them all.
Click to expand...

It depends on the curcuit:
If there is high capacitance at the output, then high drive current (paralleled circuits) improves speed.

But if you have high input source impedance, then paralleling inputs increases input capacitance and thus slowing down speed.

Klaus
 

Sorry, this is the complete circuit diagram:

optocoupler (6N137, open collector) >>> inverter gate(s) >>> MOSFET driver (TC4422A).

So the load of the inverter gate(s) would be the input stage of TC4422A. I didn't find in its datasheet the input capacitance but the input current (1uA).

Being a MOS technology, its input should be capacitive, right?
 

Hi,

You really worry about the speed of the logic....while in the signal path is an optocoupler?

Klaus
 

It's a high-speed optocoupler though and the faster inverter gate(s) will further enhance the rise/fall edges.

Anyway, we're talking about a principle here: it's better to parallel those inverter gates in this particular circuit?
 

Paralleling inverters is useful if you are e.g. driving a MOSFET. It's useless for logic load like TC4422, you're even increasing the 6N137 rise time and propagation delay by the extra load capacitance at open collector output.
 

Tis a good idea to put 10 - 47 ohms in series with each o/p if you are going to parallel them, this is due to the slightly different propagation times giving rise to slight differences in time for which some o/p's are high when others are still low, the series R's limit these peak current "shoot through's" and hence help with the lifetime of the IC...
 

Then it's better to play safe and only use one gate. Thanks everyone for your time.
 

Why are you using a Schmitt Trigger inverters IC? An ordinary inverters IC has plenty of voltage gain for pretty fast switching and often has some of its inverters paralleled to provide more output current.
But since you have a Mosfet driver you do not need more current and you need only one inverter stage. If the optocoupler has an emitter follower output then maybe you do not need an inverter.
 

Please remember that it is not always desirable to have a very fast turn-on. You can add a 10R in series with the gate to slow down the turn on. Slower turn on is sometimes desirable because it will be associated with a lower di/dt in the transformer. A conservative design is often the best under normal conditions.
 

@Audioguru:
I'm using schmitt trigger inverters because the optocoupler has an open collector output stage thus the low>high transition is quite slow.

@c_mitra:
Thanks for your advice. Actually, I'm using a 22 ohm gate series resistor but still I need a proper signal at the driver's input.
 

I want to share my recent results. I have used all 6 inverters of the 74ACT14 chip, by making parallel groups of two then putting those pairs in series.

I have choose this configuration because it was convenient for the PCB design. I've made some measurements and the results were outstanding: I've got under 25 ns rise/fall times, no overshoot or glitches, a really perfect waveform.

I don't know about paralleling a large number of inverter gates, but all these pairs of two were absolutely ok. I've made 4 identical circuits (one for every Mosfet switch) and all measurements were identical.

Thanks everyone for your kind support.
 

If you feed one gate after one inverter and another gate after four inverter, they will always be in opposite phase. Further there will be a small delay (propagation delay due to the number of gates), for the second gate. This will make sure that the two gates are never on or off at the same time!
 

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