How to evaluate a high frequency circuit implemented into the FPGA

Hello,

I have a very high speed design implemented into Virtex-5 FPGA operating at 500MHz. I am using ISE14.7. The design is fully placed and routed with no errors and warnings ! Also, the post place&route simulation results are great. Now, I am looking a way how to assure that this design works properly in reality while it is implemented into the FPGA??

Remarks:
1. The design is very high speed and no expernal probe can be connected to the pins for measurement.
2. The Virtex-5 pins are not capable to handle that frequency out for measurement since they are too slow.

Any help or hint rovided by you is cordially appreciated

Thanks all,

Regards,

Unless there was a problem with the tools implementing the design (software bugs) I've never seen a case where a correctly designed (i.e. clock domain crossing synchronization, etc) and accurately simulated (i.e. in system stimulus) design failed to operate. The timing used to meet the constraints are very conservative. You would have to end up with the worst process silicon, the lowest operational voltage allowed and the highest junction temp allowed to have a chance of something not meeting setup time and the other end of the spectrum to miss the hold time. So far I've never seen that combination.

If you lack confidence in the design, that probably means you have poor functional simulation coverage. For years now I've never run a post placed and routed design in simulation. I've only done that when I suspected the design was actually failing timing due to problems with the timing files used by the tools (which I've only seen when using the bleeding edge parts that are still ES). Mostly what I've seen in the past is that the timing improves with production timing files.

msdarvishi said:

Hello,

I have a very high speed design implemented into Virtex-5 FPGA operating at 500MHz. I am using ISE14.7. The design is fully placed and routed with no errors and warnings

Click to expand...

Assuming this also means that static timing analysis passed as well, which also presumes that you input the timing constraints properly.

Now, I am looking a way how to assure that this design works properly in reality while it is implemented into the FPGA??

Remarks:
1. The design is very high speed and no expernal probe can be connected to the pins for measurement.
2. The Virtex-5 pins are not capable to handle that frequency out for measurement since they are too slow.

Click to expand...

#1 and #2 are a little confusing. You don't really say how you are getting data in and out of the device. Just because internally you're running at 500 MHz doesn't necessarily mean that I/O is running at that speed, so how fast is the I/O running and how are the I/O setup?

On the assumption that the I/O is 'very fast' and the pins are capable of running that fast, then the next step would be to verify that the PCB design and layout is correct. With a 'very fast' interface, there will be board design routing rules as well as power distribution rules that will need to be verified.

Kevin Jennings

Kevin, I don't think the OP is attempting to interface the FPGA to the rest of their system at 500 MHz. I think the OP wants to look at internal nodes of the design (that are clocked at 500 MHz) using a scope or logic analyzer to see if the design is working as expected.

If you expect to debug your design like that I suggest you get Chipscope instead.