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What kind of logic after synthesis of this rtl

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sun_ray

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What logic will following synthesize to? Please draw the schematic

Code: 
always @ (*)
begin
if (s)
y= a;
if (r)
y=b;
end
 

Suppose, something like that...It will follow to asynchronous sequential logic.
synth.jpg
 
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    FvM

    FvM

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Seems like having unknown states, so that variants of that circuit could satisfy the code above.
 

The circuit implements a combinational latch by specification, including an unknown initial state. It's exactly corresponding to the Verilog description.
 

Because the code below is a really poor description of a circuit
Code: 
always @ (*)
begin
if (s)
y= a;
if (r)
y=b;
end
And based on the the above description, miskod gave a reasonable result of what a synthesis tool will likely implement.

This is why I really dislike people who insist on writing code where multiple lines are assigning the same signal that are not structurally within the same control statement.

How will output y gets values of input a when s=1 but r='x' or r='z' in the above schematic?
Click to expand...
It won't get the value of a because the ridiculous coding style of following one if statement with another if statement that assigns the same variable (y) ends up sequentially changing the value of y to x due to the x/z on r.

You need to read the LRM or a good book on the execution flow of Verilg.
 

How will output y gets values of input a when s=1 but r='x' or r='z' in the above schematic?
Click to expand...
Irrelevant I think, 'x' or 'z' input don't exist in synthesized hardware.
 

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