harian
Junior Member level 1
i am trying to measure current in a simple circuit consisting a voltage source and a resistor. I have written a simple verilog-a code that shorts the voltage output port to resistor input port. while simulation with spectre a error: that the branches form a loop of rigid branches (shorts) when
added to the circuit..
it is not allowed. Is there any way to do this measurement with verilo-a module.
I know ,i can read the the value with simple spectre simulation. I am willing to do this with veriloga module.
thanks
here is the schematic:
added to the circuit..
Code:
module(in,out)
I(out) <+ I(in);it is not allowed. Is there any way to do this measurement with verilo-a module.
I know ,i can read the the value with simple spectre simulation. I am willing to do this with veriloga module.
thanks
here is the schematic:
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