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Upshifting of DC Analysis curve of balanced OTA in HSPICE

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bharat_tangudu

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I am trying to simulate the balanced OTA in HSPICE.

I took one paper as a reference for transistor parameters and bias current, etc. paper can be downloaded from this link https://ieeexplore.ieee.org/xpls/abs_all.jsp?arnumber=5746529&tag=1

Though i followed that paper, i was not getting the proper DC characteristics which is shifting toward 1st quadrant. I tried all the possible ways to shift the curve. But i was not able to solve the problem. Can someone correct me in solving this problem either by modifying the netlist if there is any mistake in that or by providing some material to clear this problem????

I am attaching the schematic of balanced OTA structure and its DC characteristics.

Also, I am copying the code here

**broken link removed**

**broken link removed**

Code:
----------------------------------------
Balance OTA

M1 vg4 vin+ 4 0 nmos l=0.2u w=20u
M2 vg3 vin- 4 0 nmos l=0.2u w=20u
M3 vg3 vg3 1 1 pmos l=0.2u w=15u
M4 vg4 vg4 1 1 pmos l=0.2u w=15u
M5 3 vg3 1 1 pmos l=0.2u w=15u
M6 5 vg4 1 1 pmos l=0.2u w=15u
M7 3 3 0 0 nmos l=1u w=5u
M8 5 3 0 0 nmos l=1u w=5u
M9 2 2 0 0 nmos l=1u w=15u
M10 4 2 0 0 nmos l=1u w=15u

Ib 1 2 dc 40uA
Vnull 5 0 dc 0v
Vdd 1 0 dc 1.8V

Vi1 vin+ 0 dc 0v sin(0v 100mv 10khz)
Vi2 vin- 0 dc 0.9v sin(0v 50mv 10khz)


.dc Vi1 -1 1 0.001
.op
.option post 
.option nomod
.probe
.end
------------------------------------
* Predictive Technology Model Beta Version
* 180nm NMOS SPICE Parametersv (normal one)
*

.model NMOS NMOS
+Level = 49

+Lint = 4.e-08 Tox = 4.e-09 
+Vth0 = 0.3999 Rdsw = 250 

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1
+Xj= 6.0000000E-08         Nch= 5.9500000E+17 
+lln= 1.0000000            lwn= 1.0000000              wln= 0.00
+wwn= 0.00                 ll= 0.00
+lw= 0.00                  lwl= 0.00                   wint= 0.00
+wl= 0.00                  ww= 0.00                    wwl= 0.00
+Mobmod=  1                binunit= 2                  xl=  0
+xw=  0                    binflag=  0
+Dwg= 0.00                 Dwb= 0.00 

+K1= 0.5613000               K2= 1.0000000E-02 
+K3= 0.00                  Dvt0= 8.0000000             Dvt1= 0.7500000 
+Dvt2= 8.0000000E-03       Dvt0w= 0.00                 Dvt1w= 0.00 
+Dvt2w= 0.00               Nlx= 1.6500000E-07          W0= 0.00 
+K3b= 0.00                 Ngate= 5.0000000E+20 

+Vsat= 1.3800000E+05       Ua= -7.0000000E-10          Ub= 3.5000000E-18 
+Uc= -5.2500000E-11        Prwb= 0.00 
+Prwg= 0.00                Wr= 1.0000000               U0= 3.5000000E-02 
+A0= 1.1000000             Keta= 4.0000000E-02         A1= 0.00 
+A2= 1.0000000             Ags= -1.0000000E-02         B0= 0.00 
+B1= 0.00 

+Voff= -0.12350000          NFactor= 0.9000000          Cit= 0.00 
+Cdsc= 0.00                Cdscb= 0.00                 Cdscd= 0.00 
+Eta0= 0.2200000           Etab= 0.00                  Dsub= 0.8000000 

+Pclm= 5.0000000E-02       Pdiblc1= 1.2000000E-02      Pdiblc2= 7.5000000E-03 
+Pdiblcb= -1.3500000E-02   Drout= 1.7999999E-02        Pscbe1= 8.6600000E+08 
+Pscbe2= 1.0000000E-20     Pvag= -0.2800000            Delta= 1.0000000E-02 
+Alpha0= 0.00              Beta0= 30.0000000 

+kt1= -0.3700000           kt2= -4.0000000E-02         At= 5.5000000E+04 
+Ute= -1.4800000           Ua1= 9.5829000E-10          Ub1= -3.3473000E-19 
+Uc1= 0.00                 Kt1l= 4.0000000E-09         Prt= 0.00 

+Cj= 0.00365               Mj= 0.54                    Pb= 0.982
+Cjsw= 7.9E-10             Mjsw= 0.31                  Php= 0.841
+Cta= 0                    Ctp= 0                      Pta= 0
+Ptp= 0                    JS=1.50E-08                 JSW=2.50E-13
+N=1.0                     Xti=3.0                     Cgdo=2.786E-10
+Cgso=2.786E-10            Cgbo=0.0E+00                Capmod= 2
+NQSMOD= 0                 Elm= 5                      Xpart= 1
+Cgsl= 1.6E-10             Cgdl= 1.6E-10               Ckappa= 2.886
+Cf= 1.069e-10             Clc= 0.0000001              Cle= 0.6
+Dlc= 4E-08                Dwc= 0                      Vfbcv= -1


*
* Predictive Technology Model Beta Version
* 180nm PMOS SPICE Parametersv (normal one)
*

.model PMOS PMOS
+Level = 49

+Lint = 3.e-08 Tox = 4.2e-09 
+Vth0 = -0.42 Rdsw = 450 

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1
+Xj= 7.0000000E-08         Nch= 5.9200000E+17 
+lln= 1.0000000            lwn= 1.0000000              wln= 0.00
+wwn= 0.00                 ll= 0.00
+lw= 0.00                  lwl= 0.00                   wint= 0.00
+wl= 0.00                  ww= 0.00                    wwl= 0.00
+Mobmod=  1                binunit= 2                  xl= 0.00
+xw= 0.00                  
+binflag=  0               Dwg= 0.00                   Dwb= 0.00 

+ACM= 0                    ldif=0.00                   hdif=0.00
+rsh= 0                    rd= 0                       rs= 0
+rsc= 0                    rdc= 0

+K1= 0.5560000             K2= 0.00 
+K3= 0.00                  Dvt0= 11.2000000            Dvt1= 0.7200000 
+Dvt2= -1.0000000E-02      Dvt0w= 0.00                 Dvt1w= 0.00 
+Dvt2w= 0.00               Nlx= 9.5000000E-08          W0= 0.00 
+K3b= 0.00                 Ngate= 5.0000000E+20 

+Vsat= 1.0500000E+05       Ua= -1.2000000E-10          Ub= 1.0000000E-18 
+Uc= -2.9999999E-11        Prwb= 0.00 
+Prwg= 0.00                Wr= 1.0000000               U0= 8.0000000E-03 
+A0= 2.1199999             Keta= 2.9999999E-02         A1= 0.00 
+A2= 0.4000000             Ags= -0.1000000             B0= 0.00 
+B1= 0.00 

+Voff= -6.40000000E-02      NFactor= 1.4000000          Cit= 0.00 
+Cdsc= 0.00                Cdscb= 0.00                 Cdscd= 0.00 
+Eta0= 8.5000000           Etab= 0.00                  Dsub= 2.8000000 

+Pclm= 2.0000000           Pdiblc1= 0.1200000          Pdiblc2= 8.0000000E-05 
+Pdiblcb= 0.1450000        Drout= 5.0000000E-02        Pscbe1= 1.0000000E-20 
+Pscbe2= 1.0000000E-20     Pvag= -6.0000000E-02        Delta= 1.0000000E-02 
+Alpha0= 0.00              Beta0= 30.0000000 

+kt1= -0.3700000           kt2= -4.0000000E-02         At= 5.5000000E+04 
+Ute= -1.4800000           Ua1= 9.5829000E-10          Ub1= -3.3473000E-19 
+Uc1= 0.00                 Kt1l= 4.0000000E-09         Prt= 0.00 

+Cj= 0.00138               Mj= 1.05                    Pb= 1.24
+Cjsw= 1.44E-09            Mjsw= 0.43                  Php= 0.841
+Cta= 0.00093              Ctp= 0                      Pta= 0.00153
+Ptp= 0                    JS=1.50E-08                 JSW=2.50E-13
+N=1.0                     Xti=3.0                     Cgdo=2.786E-10
+Cgso=2.786E-10            Cgbo=0.0E+00                Capmod= 2
+NQSMOD= 0                 Elm= 5                      Xpart= 1
+Cgsl= 1.6E-10             Cgdl= 1.6E-10               Ckappa= 2.886
+Cf= 1.058e-10             Clc= 0.0000001              Cle= 0.6
+Dlc= 3E-08                Dwc= 0  
---------------------------------------------------------------------
I am new to the analog area and i really want to work in analog circuits. Please help me in solving this issue.
 
Last edited by a moderator:

Your attachments currently are "invalid". Try and attach them once more pls.
 

Sorry for the inconvenience. The attachments are again uploaded in this reply.
Please look at this.
1.JPG2.jpg
 

Without having tried myself, here a few notes and suggestions:

Your output short circuit voltage source
Code:
Vnull 5 0 dc 0v
… forces the output to 0V (GND), which doesn’t fit into a reasonable output range; change it to vdd/2 = 0.9V .

The positive input
Code:
Vi1 vin+ 0 dc 0v
… also is forced to GND, which probably was thought to force the output to 0V (which doesn’t fit, s. above) in a unity gain circuit (which isn’t the case in your circuit); also change it to 0.9V .

For your supply voltage Vdd=1.8V the sweep range of ±1V is too high, limit it to about ±0.5V :
Code:
.dc Vi1 -0.5 0.5 0.001

Then try again and come back with your results.
 

With the suggestions mentioned in the above comment, i modified the netlist and the simulated again. But the results obtained are same as before only.

For the reference, i am copying the modified code and attaching the obtained DC characteristics in this comment.

DC.jpg

Code:
--------------------------------------
Balanced OTA

M1 vg4 vin+ 4 0 nmos l=1u w=20u
M2 vg3 vin- 4 0 nmos l=1u w=20u
M3 vg3 vg3 1 1 pmos l=0.2u w=15u
M4 vg4 vg4 1 1 pmos l=0.2u w=15u
M5 3 vg3 1 1 pmos l=0.2u w=15u
M6 5 vg4 1 1 pmos l=0.2u w=15u
M7 3 3 0 0 nmos l=1u w=5u
M8 5 3 0 0 nmos l=1u w=5u
M9 2 2 0 0 nmos l=1u w=15u
M10 4 2 0 0 nmos l=1u w=15u

Ib 1 2 dc 40uA
Vo 5 0 dc 0.9v
Vdd 1 0 dc 1.8V

.lib "ptm.sp" cmos_models

Vi1 vin+ 0 dc 0.9v sin(0v 100mv 10khz)
Vi2 vin- 0 dc 0.9v sin(0v 50mv 10khz)


.dc Vi1 -0.5 0.5 0.001
.op
.option post 
.option nomod
.probe
.end
-------------------------------------
.lib cmos_models

* Predictive Technology Model Beta Version
* 180nm NMOS SPICE Parametersv (normal one)
*

.model NMOS NMOS
+Level = 49

+Lint = 4.e-08 Tox = 4.e-09 
+Vth0 = 0.3999 Rdsw = 250 

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1
+Xj= 6.0000000E-08         Nch= 5.9500000E+17 
+lln= 1.0000000            lwn= 1.0000000              wln= 0.00
+wwn= 0.00                 ll= 0.00
+lw= 0.00                  lwl= 0.00                   wint= 0.00
+wl= 0.00                  ww= 0.00                    wwl= 0.00
+Mobmod=  1                binunit= 2                  xl=  0
+xw=  0                    binflag=  0
+Dwg= 0.00                 Dwb= 0.00 

+K1= 0.5613000               K2= 1.0000000E-02 
+K3= 0.00                  Dvt0= 8.0000000             Dvt1= 0.7500000 
+Dvt2= 8.0000000E-03       Dvt0w= 0.00                 Dvt1w= 0.00 
+Dvt2w= 0.00               Nlx= 1.6500000E-07          W0= 0.00 
+K3b= 0.00                 Ngate= 5.0000000E+20 

+Vsat= 1.3800000E+05       Ua= -7.0000000E-10          Ub= 3.5000000E-18 
+Uc= -5.2500000E-11        Prwb= 0.00 
+Prwg= 0.00                Wr= 1.0000000               U0= 3.5000000E-02 
+A0= 1.1000000             Keta= 4.0000000E-02         A1= 0.00 
+A2= 1.0000000             Ags= -1.0000000E-02         B0= 0.00 
+B1= 0.00 

+Voff= -0.12350000          NFactor= 0.9000000          Cit= 0.00 
+Cdsc= 0.00                Cdscb= 0.00                 Cdscd= 0.00 
+Eta0= 0.2200000           Etab= 0.00                  Dsub= 0.8000000 

+Pclm= 5.0000000E-02       Pdiblc1= 1.2000000E-02      Pdiblc2= 7.5000000E-03 
+Pdiblcb= -1.3500000E-02   Drout= 1.7999999E-02        Pscbe1= 8.6600000E+08 
+Pscbe2= 1.0000000E-20     Pvag= -0.2800000            Delta= 1.0000000E-02 
+Alpha0= 0.00              Beta0= 30.0000000 

+kt1= -0.3700000           kt2= -4.0000000E-02         At= 5.5000000E+04 
+Ute= -1.4800000           Ua1= 9.5829000E-10          Ub1= -3.3473000E-19 
+Uc1= 0.00                 Kt1l= 4.0000000E-09         Prt= 0.00 

+Cj= 0.00365               Mj= 0.54                    Pb= 0.982
+Cjsw= 7.9E-10             Mjsw= 0.31                  Php= 0.841
+Cta= 0                    Ctp= 0                      Pta= 0
+Ptp= 0                    JS=1.50E-08                 JSW=2.50E-13
+N=1.0                     Xti=3.0                     Cgdo=2.786E-10
+Cgso=2.786E-10            Cgbo=0.0E+00                Capmod= 2
+NQSMOD= 0                 Elm= 5                      Xpart= 1
+Cgsl= 1.6E-10             Cgdl= 1.6E-10               Ckappa= 2.886
+Cf= 1.069e-10             Clc= 0.0000001              Cle= 0.6
+Dlc= 4E-08                Dwc= 0                      Vfbcv= -1


*
* Predictive Technology Model Beta Version
* 180nm PMOS SPICE Parametersv (normal one)
*

.model PMOS PMOS
+Level = 49

+Lint = 3.e-08 Tox = 4.2e-09 
+Vth0 = -0.42 Rdsw = 450 

+lmin=1.8e-7 lmax=1.8e-7 wmin=1.8e-7 wmax=1.0e-4 Tref=27.0 version =3.1
+Xj= 7.0000000E-08         Nch= 5.9200000E+17 
+lln= 1.0000000            lwn= 1.0000000              wln= 0.00
+wwn= 0.00                 ll= 0.00
+lw= 0.00                  lwl= 0.00                   wint= 0.00
+wl= 0.00                  ww= 0.00                    wwl= 0.00
+Mobmod=  1                binunit= 2                  xl= 0.00
+xw= 0.00                  
+binflag=  0               Dwg= 0.00                   Dwb= 0.00 

+ACM= 0                    ldif=0.00                   hdif=0.00
+rsh= 0                    rd= 0                       rs= 0
+rsc= 0                    rdc= 0

+K1= 0.5560000             K2= 0.00 
+K3= 0.00                  Dvt0= 11.2000000            Dvt1= 0.7200000 
+Dvt2= -1.0000000E-02      Dvt0w= 0.00                 Dvt1w= 0.00 
+Dvt2w= 0.00               Nlx= 9.5000000E-08          W0= 0.00 
+K3b= 0.00                 Ngate= 5.0000000E+20 

+Vsat= 1.0500000E+05       Ua= -1.2000000E-10          Ub= 1.0000000E-18 
+Uc= -2.9999999E-11        Prwb= 0.00 
+Prwg= 0.00                Wr= 1.0000000               U0= 8.0000000E-03 
+A0= 2.1199999             Keta= 2.9999999E-02         A1= 0.00 
+A2= 0.4000000             Ags= -0.1000000             B0= 0.00 
+B1= 0.00 

+Voff= -6.40000000E-02      NFactor= 1.4000000          Cit= 0.00 
+Cdsc= 0.00                Cdscb= 0.00                 Cdscd= 0.00 
+Eta0= 8.5000000           Etab= 0.00                  Dsub= 2.8000000 

+Pclm= 2.0000000           Pdiblc1= 0.1200000          Pdiblc2= 8.0000000E-05 
+Pdiblcb= 0.1450000        Drout= 5.0000000E-02        Pscbe1= 1.0000000E-20 
+Pscbe2= 1.0000000E-20     Pvag= -6.0000000E-02        Delta= 1.0000000E-02 
+Alpha0= 0.00              Beta0= 30.0000000 

+kt1= -0.3700000           kt2= -4.0000000E-02         At= 5.5000000E+04 
+Ute= -1.4800000           Ua1= 9.5829000E-10          Ub1= -3.3473000E-19 
+Uc1= 0.00                 Kt1l= 4.0000000E-09         Prt= 0.00 

+Cj= 0.00138               Mj= 1.05                    Pb= 1.24
+Cjsw= 1.44E-09            Mjsw= 0.43                  Php= 0.841
+Cta= 0.00093              Ctp= 0                      Pta= 0.00153
+Ptp= 0                    JS=1.50E-08                 JSW=2.50E-13
+N=1.0                     Xti=3.0                     Cgdo=2.786E-10
+Cgso=2.786E-10            Cgbo=0.0E+00                Capmod= 2
+NQSMOD= 0                 Elm= 5                      Xpart= 1
+Cgsl= 1.6E-10             Cgdl= 1.6E-10               Ckappa= 2.886
+Cf= 1.058e-10             Clc= 0.0000001              Cle= 0.6
+Dlc= 3E-08                Dwc= 0                      Vfbcv= -1
----------------------------------------------------------------------------------

please have a look at this and correct me if i am wrong anywhere in the netlist.

Along with this, i have one more question to ask...
what would be the best element (that should be connected) to observe the current passing through high impedance node? ( In the above case, output node is high impedance node)
 
Last edited by a moderator:

... please have a look at this and correct me if i am wrong anywhere in the netlist.
Your changes are correct.

... the results obtained are same as before only.
Sorry for that. In this case I'd guess your OTA isn't working in a correct operation point. Did you check this before? If not, I'd suggest the following: Remove (comment with a * in front) the output short circuit voltage source Vo and note the DC output voltage when both inputs are @ Vdd/2 : it should also be about Vdd/2 . If not, the OTA isn't in its correct operation point, and the W/L ratios of some MOSFETs need to be changed.

... what would be the best element (that should be connected) to observe the current passing through high impedance node? ( In the above case, output node is high impedance node)

The current passing through a high impedance node should be observed by passing it through a low impedance element: a short circuit at best - and that's exactly what you did with your short circuit voltage source Vo. SPICE voltage sources always have zero resistance. One more possibility in SPICE would be a zero-Ohm resistor.
 

In this case I'd guess your OTA isn't working in a correct operation point. Did you check this before? If not, I'd suggest the following: Remove (comment with a * in front) the output short circuit voltage source Vo and note the DC output voltage when both inputs are @ Vdd/2 : it should also be about Vdd/2 . If not, the OTA isn't in its correct operation point, and the W/L ratios of some MOSFETs need to be changed.

As you suggested i tested DC operating point status at the output node. It was coming around 0.65V. I dont know whether it is acceptable or not. I tried to increase this value to VDD/2 by adjusting the W/L ratios of some transistors randomly (following some basic rules like width of pmos should be more than twice the width of nmos) . with this, i was able to increase the value around 20mV only.

I want to know W/L ratios of which transistor(in the given circuit) should be changed so that our design requirements would be achieved?? Is this a random procedure or having any design rules? If there are any design rules for analog design, can you provide some material related to this?
 

As you suggested i tested DC operating point status at the output node. It was coming around 0.65V. I dont know whether it is acceptable or not. I tried to increase this value to VDD/2 by adjusting the W/L ratios of some transistors randomly (following some basic rules like width of pmos should be more than twice the width of nmos) . with this, i was able to increase the value around 20mV only.

0.65V static output voltage (for both inputs at 0.9V) is too low, but not so bad at all. Could you provide the output voltage plot vs. input voltage sweep? Probably an input voltage sweep of ±10mV would be enough.

I want to know W/L ratios of which transistor(in the given circuit) should be changed so that our design requirements would be achieved?? Is this a random procedure or having any design rules? If there are any design rules for analog design, can you provide some material related to this?

I think you really should learn analog circuit design from scratch. I'd suggest to study one of these textbooks.
 

0.65V static output voltage (for both inputs at 0.9V) is too low, but not so bad at all. Could you provide the output voltage plot vs. input voltage sweep? Probably an input voltage sweep of ±10mV would be enough.

Thank you for suggesting the textbooks to lay the foundation in analog circuit design. I will definitely learn the analog concepts from the above mentioned books.

The below is the output voltage plot sweeping the input voltage ±10mV. please look at the plot attached here. output voltage.jpg
 

The below is the output voltage plot sweeping the input voltage ±10mV. please look at the plot attached here.
Means there's insufficient gain - wrong operation points / wrong W/L ratios.

Then use ±500mV input voltage sweep again, this should at least show some output voltage change for the pos. side of the sweep.
But then there's something wrong with the operation points of the other transistors, too.

To go on, you should show a schematic (not the netlist) with DC operation points of all transistors, if possible with their W & L dimensions.
DC simulation again with both inputs @ Vdd/2 , no sweep necessary.
 

I saw that some change in output voltage for the positive side of the input sweep. Below attached file is the plot for change in output input sweep of ±500mV.

Vout.jpg

I checked the DC operation points of all MOSFETS, which went to saturation region.
For the reference, i am attaching schematic of circuit (with W/L ratios) and operation point information taken from output generated file (.lis file) of circuit

IMG_1332.JPG

operation point information
Code:
--------------------------
 ******  operating point information      tnom=  25.000 temp=  25.000          
 ******  
 ***** operating point status is all       simulation time is     0.     
    node    =voltage      node    =voltage      node    =voltage

 +0:1       =   1.8000  0:2       = 566.7831m 0:3       = 649.8354m
 +0:4       = 316.5120m 0:5       = 649.8354m 0:vg3     =   1.3747 
 +0:vg4     =   1.3747  0:vin+    = 900.0000m 0:vin-    = 900.0000m


 ****  voltage sources

 subckt                                   
 element  0:vdd      0:vi1      0:vi2     
  volts      1.8000   900.0000m  900.0000m
  current -139.7966u    0.         0.     
  power    251.6339u    0.         0.     

     total voltage source power dissipation=  251.6339u       watts



 ***** current sources

 subckt             
 element  0:ib      
  volts      1.2332 
  current   40.0000u
  power    -49.3287u


     total current source power dissipation= -49.3287u       watts


 **** mosfets


 subckt                                                                    
 element  0:m1       0:m2       0:m3       0:m4       0:m5       0:m6      
 model    0:nmos     0:nmos     0:pmos     0:pmos     0:pmos     0:pmos    
 region     Saturati   Saturati   Saturati   Saturati   Saturati   Saturati
  id        19.4128u   19.4128u  -19.4128u  -19.4128u  -30.4855u  -30.4855u
  ibs        0.         0.         0.         0.         0.         0.     
  ibd        0.         0.         0.         0.         0.         0.     
  vgs      583.4880m  583.4880m -425.2508m -425.2508m -425.2508m -425.2508m
  vds        1.0582     1.0582  -425.2508m -425.2508m   -1.1502    -1.1502 
  vbs     -316.5120m -316.5120m    0.         0.         0.         0.     
  vth      537.6823m  537.6823m -358.8923m -358.8923m -357.3252m -357.3252m
  vdsat     89.6511m   89.6511m  -74.1319m  -74.1319m  -74.8970m  -74.8970m
  vod       45.8057m   45.8057m  -66.3585m  -66.3585m  -67.9257m  -67.9257m
  beta       6.1002m    6.1002m    7.0426m    7.0426m    7.0434m    7.0434m
  gam eff  539.1795m  539.1795m  556.0000m  556.0000m  556.0000m  556.0000m
  gm       317.9270u  317.9270u  377.3138u  377.3138u  580.1874u  580.1874u
  gds        2.2079u    2.2079u   14.9493u   14.9493u   15.6749u   15.6749u
  gmb       87.2685u   87.2685u   44.0806u   44.0806u   68.0618u   68.0618u
  cdtot     10.2352f   10.2352f    8.0886f    8.0886f    7.4829f    7.4829f
  cgtot    128.4379f  128.4379f   29.6842f   29.6842f   29.1381f   29.1381f
  cstot    117.8828f  117.8828f   19.3779f   19.3779f   19.4526f   19.4526f
  cbtot     35.0287f   35.0287f    4.6581f    4.6581f    4.6558f    4.6558f
  cgs      105.6969f  105.6969f   18.3211f   18.3211f   18.3791f   18.3791f
  cgd       10.2320f   10.2320f    8.0508f    8.0508f    7.4535f    7.4535f



 subckt                                              
 element  0:m7       0:m8       0:m9       0:m10     
 model    0:nmos     0:nmos     0:nmos     0:nmos    
 region     Saturati   Saturati   Saturati   Saturati
  id        30.4855u   30.4855u   40.0000u   38.8256u
  ibs        0.         0.         0.         0.     
  ibd        0.         0.         0.         0.     
  vgs      649.8354m  649.8354m  566.7831m  566.7831m
  vds      649.8354m  649.8354m  566.7831m  316.5120m
  vbs        0.         0.         0.         0.     
  vth      448.2914m  448.2914m  448.2914m  448.2914m
  vdsat    189.8164m  189.8164m  132.0119m  132.0119m
  vod      201.5440m  201.5440m  118.4916m  118.4916m
  beta       1.5506m    1.5506m    4.7508m    4.7508m
  gam eff  542.2548m  542.2548m  542.2548m  542.2548m
  gm       248.5346u  248.5346u  474.1196u  461.6725u
  gds        2.8994u    2.8994u    4.4660u    5.3177u
  gmb       79.0907u   79.0907u  148.5614u  144.5382u
  cdtot      2.7329f    2.7329f    8.1684f    8.6681f
  cgtot     37.0161f   37.0161f  109.5963f  109.9390f
  cstot     36.9989f   36.9989f  108.6456f  108.5026f
  cbtot     10.1720f   10.1720f   30.6867f   30.7398f
  cgs       32.1915f   32.1915f   94.4240f   94.5974f
  cgd        2.7120f    2.7120f    8.1237f    8.3721f
 

Thank you for your detailed response! I've got a few remarks and questions:

1) Input to output voltage plot: not too bad. Gain only about 20 (which is too low) and shifted to pos. voltage as your output current plot. Could you provide one more plot with an input voltage of ±125mV ?

2) What strikes me is the fact that (in DC operation point) the output voltage (node 5) is exactly the same as the gate voltage at M7/M8 (node 3). But it can't be a short circuit - see your output plot. Such an exact coincidence?

3) Did you take over the W/L ratios from the article? If so, do you (have to) cling very closely to these W/L ratios? If so, I think we can achieve the back-shifting with not too many changes.

If not, I'd advice you to use new W/L ratios at many transistors - as soon as I've got the time to simulate your circuit. Reasons for such changes:

a) M10 need not operate in saturation region - costs too much voltage drop. Triode region is ok.
b) M1/M2 are working in (strong) moderate inversion (IC≈2); they should have much higher W/L ratio to achieve a higher gain.
c) all the current sources (apart M3/M4) should work in strong inversion - much lower W/L ratios needed for their current
d) M7/M8 should get their bias (gate) voltage from M9/M10
 

1) Input to output voltage plot: not too bad. Gain only about 20 (which is too low) and shifted to pos. voltage as your output current plot. Could you provide one more plot with an input voltage of ±125mV ?

2) What strikes me is the fact that (in DC operation point) the output voltage (node 5) is exactly the same as the gate voltage at M7/M8 (node 3). But it can't be a short circuit - see your output plot. Such an exact coincidence?

3) Did you take over the W/L ratios from the article? If so, do you (have to) cling very closely to these W/L ratios? If so, I think we can achieve the back-shifting with not too many changes.

1) I am attaching the DC plot with input voltage sweep of ±125mV.
small_voltage_sweep.jpg

2)Yeah, i noticed that the voltage at node5 and node3 are same.

3)I took the W/L ratios of all MOSFETs from the article only. I strictly limited to these values as i wanted to replicate the results. What were the changes i made are library files. "UMC 180nm" model files are being used in that article and i used "PTM model files"

a) M10 need not operate in saturation region - costs too much voltage drop. Triode region is ok.
b) M1/M2 are working in (strong) moderate inversion (IC≈2); they should have much higher W/L ratio to achieve a higher gain.
c) all the current sources (apart M3/M4) should work in strong inversion - much lower W/L ratios needed for their current
d) M7/M8 should get their bias (gate) voltage from M9/M10

Do you want me to change the modifications to the existing circuit (dimensions taken from article) or to our designed circuit (dimensions not taken from article)?
 

1) I am attaching the DC plot with input voltage sweep of ±125mV.
Looks reasonable, apart from the shifting. Shows that the OTA operates "in principle", but has a rather low DC gain (≈20 ; should have 100 .. 1000), probably because of operation point shifting - and not optimal design (which is not up to you, of course).

Do you want me to change the modifications to the existing circuit (dimensions taken from article) or to our designed circuit (dimensions not taken from article)?
Actually this is your choice. I'd suggest, however, first to repair this nasty shifting from your design - as it is now -, then repeat your simulations.
Let's see how high the DC gain will rise after repair (I fear: not too much). After this I could still help you for a better design - if you want.

Repair of the shifting: The aim is to get the idle DC output voltage to Vdd/2 . This is necessary 1. to allow for DC feedback to the neg. input, which is necessary for a real design, and also facilitates the test bench for further analysis - and 2. to shift back the input-to-output characteristic into the center (Vdd/2) - that's what you wanted in the first place ;-) .

The simplest - not the most elegant, though feasible - way to achieve this is to trim M5's W/L ratio a little bit down - a few percent are enough. In my simulation, a -6% change is enough:
180nm_OTA_v13.png.

Note: I'm using a different (low level) model file, still with the main 180nm process parameters, especially with your Vth0 values, and a different SPICE simulator. Hence your own results will deviate slightly from mine.

My results show a DC gain of about 170 , which is probably a good value for this design. Now try a similar change - you will probably need a little bit different percent change, but this should work anyway. Then come back with your Vout vs. Vin & Iout vs. Vin curves.
 

Attachments

  • OTA_v13.png
    OTA_v13.png
    135.1 KB · Views: 102
Thank you very much for the brief reply with your results.

Repair of the shifting: The aim is to get the idle DC output voltage to Vdd/2 . This is necessary 1. to allow for DC feedback to the neg. input, which is necessary for a real design, and also facilitates the test bench for further analysis - and 2. to shift back the input-to-output characteristic into the center (Vdd/2) - that's what you wanted in the first place ;-) .

The simplest - not the most elegant, though feasible - way to achieve this is to trim M5's W/L ratio a little bit down - a few percent are enough. In my simulation, a -6% change is enough:


Note: I'm using a different (low level) model file, still with the main 180nm process parameters, especially with your Vth0 values, and a different SPICE simulator. Hence your own results will deviate slightly from mine.

My results show a DC gain of about 170 , which is probably a good value for this design. Now try a similar change - you will probably need a little bit different percent change, but this should work anyway. Then come back with your Vout vs. Vin & Iout vs. Vin curves.


In my simulations, i cut down the W/L rato of M5 by 10% which gave me reasonable shift in the curve but the gain of the circuit did not increase like what happened in your simulation.
I am attaching the graph of Vout vs Vin.

New_DC.jpg
 

... but the gain of the circuit did not increase like what happened in your simulation.

Let's see how high the DC gain will rise after repair (I fear: not too much).

Your DC gain initially was about 20, now it is about 40, measured between Voff = ±10mV . The fact that the DC gain of your circuit didn't rise as much as that of mine probably is due to our different models. Did you check that your transistors still work in saturation region (at least those which are responsible for gain)?
 

Yeah..all the transistors are in saturation region except the PMOS transistor in output stage (M6) which is in linear region.
 

... except the PMOS transistor in output stage (M6) which is in linear region.

Actually in quiescent state (Vout = Vdd/2) this isn't possible. Only outside of the output common mode range (OCMR), and this is no working range.
 

Can you guide what should be done in order to solve this problem?
 

Sure, I promised. But you should tell what your problem is. You didn't respond to my last post.
 

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