davidyu
Junior Member level 2
memory floorplan
I have a chip require to place the 12 memory macro, one inisist place all of the memeory together and only the routing channel is reserved between the memory. But I think that the more space should be given to place some stdcells for meet the timing constraint. if only the routing channel is reserved, maybe the very long wire is required to stride over some memory macro to connect with the far away memory. the process is 0.18 cmos, area 4*4, total memory is 76Kbyte. How do u think about it with ur experience?
I have a chip require to place the 12 memory macro, one inisist place all of the memeory together and only the routing channel is reserved between the memory. But I think that the more space should be given to place some stdcells for meet the timing constraint. if only the routing channel is reserved, maybe the very long wire is required to stride over some memory macro to connect with the far away memory. the process is 0.18 cmos, area 4*4, total memory is 76Kbyte. How do u think about it with ur experience?