Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Generating delayed clock (frequency dependent)

Status
Not open for further replies.
M

mordak

Member level 5
Joined
Mar 8, 2013
Messages
82
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Location
Neverland
Activity points
2,134
Generating delayed clock (frequnecy dependent)

Hi,

I was trying to make a delay version of a clock signal which is, say 1/5th of the period delayed compared to the original signal. If I generate this delayed clock with chain of inverter gates, that would work. However, if I change the the input frequency, that delay would stay constant regardless of the input frequency. I wonder how I can make a delayed clock that changes with the input frequency.

Thanks
 

Re: Generating delayed clock (frequnecy dependent)

Synchronized N=5 ring oscillator as part of a PLL, pick
the tap you like?
 

Re: Generating delayed clock (frequnecy dependent)

crutschow said:
What is the frequency range of the clock?
Click to expand...
It's varying from 15 MHz to 150 MHz, with 10 steps.

dick_freebird said:
Synchronized N=5 ring oscillator as part of a PLL, pick
the tap you like?
Click to expand...
It's just a small digital part of a big mixed-mode circuit, which I prefer to avoid using any complex circuit. So I hope there would be a way to do it without using a PLL.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top