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Clock uncertainty in FPGA tools

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Dinoc

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Hi all,

I have a doubt related to clock uncertainty in the FPGA design flow using (for example) Quartus.
Why should someone want to overwrite the clock uncertainty generated by "derive_clock_uncertainty" using the "set_clock_uncertainty"?
Isn't the derived uncertainty enough precise to be trusted by the designer?

Thanks in advance
 

According to the documentation derive_clock_uncertainty propagates the uncertainty to the destination setup and hold calculations.

The set_clock_uncertainty is used to set the uncertainty of clocks coming in on the pins of the device using a virtual clock, i.e. the oscillator on the board driving the clock.
 
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    Dinoc

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Thanks for the answer :thumbsup:
Anyway, the result of "derive_clock_uncertainty" is a set of "set_clock_uncertainty" assigned to each internal (PLL-generated) clock.
My doubt was how are these uncertainties extracted? Does the tool take into account the FPGA technology (and the routing) to assign them?
I see your point on virtual clocks but you can also use the set_clock_uncertainty for internal clocks, not only the one coming in on the input pins.
I don't see any reason of doing that internally adding uncertainty to the routing-aware uncertainties.
Do I miss any point?

Thanks agin
 

When deciding what's appropriate in a SDC setup, I primarily refer to Ryan Scovilles "TimeQuest User Guide" see .

Secondly the Quartus SDC reference manual and the Synopsis timing constraints user guide.

The former says that set_clock_certainty would be rarely used in a typical design flow.

If at all, I would rather use the -add option than ignoring the previously derived uncertainty numbers.
 
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    Dinoc

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FvM said:
The former says that set_clock_certainty would be rarely used in a typical design flow.

If at all, I would rather use the -add option than ignoring the previously derived uncertainty numbers.
Click to expand...

Thanks, this was exactly what I was guessing, especially when the Scovilles' guide says "most designs never use this constraint (set_clock_uncertainty) and rely on derive_clock_uncertainty, which models all internal clock effects for the user".

Any other opinion about the topic is welcome.
 

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