[SOLVED] communication between quad core ARM in an ASIC and dual core ARM on a FPGA ZC7020

Hello,

I plan to establish communication to read write between two processors. On one side is a quad core ARM cortex A9 processor on a ASIC (MCIMX6) and on the other side is a FPGA (ZC7020). I don't have any PCIe hard ports on the FPGA side. So there are two ways of establishing communication between these two processsors. If I intend to retain ZC7020, I have 2 options

1) Use a serial bus interface like I2C or SPI (data transfer rate is very less about 10 Mb/sec
2) Use a shared memory between the two processors using AMBA AXI interconnect and establish this connection.

I would like to know what speed would the 2nd method yield and how to execute this shared memory concept in vivado? Please give me a reference article for the same. I require about 1.5 Gb/sec speed between the two processors.

Else I may have to change the device to ZC7015 and buy a hard core PCIe IP and establish the communication which ofcourse is very expensive. If I want to do a soft core PCIe on ZC7015, what are the steps I need to follow.

Thanks,
Sunayana

1.5 Gbit/s translates to a moderate speed on an e.g. 32 bit wide parallel bus and is surely feasible. I would consider a dual port RAM implemented in the FPGA.

I have two OSes each on the quad core and the dual core processor. They are linux embedded OSes. Will that be a concern? How do I interface the processors using a parallel bus? Is it a physical connection or does it require programming?

Sunayana Chakradhar said:

I have two OSes each on the quad core and the dual core processor. They are linux embedded OSes. Will that be a concern? How do I interface the processors using a parallel bus? Is it a physical connection or does it require programming?

Click to expand...

It will require a driver in each OS, as they will need to be able to talk to the addresses in the RAM.
1.5Gbs is certainly ok in the FPGA - the limiting factor might be the processors and the software overheads needed to do the memory IOs

Okay, but the OS's driver would require a AXI bus to run on if i am right? So if i understand it right, i would require a physical cable between the two processors which are for example connected to the GPIO pins on either sides. These GPIO ports on the PL need to be interconnected with the PS using AXI master-slave methodology. In order to connect it to a DDR memory, i can use the AXI master on the PL.