ishan.dalal
Newbie level 5
Hi,
I am working on converting a VHDL code which is heavy on records structures usage to verilog. It's a highly parameterized code using packages. I am also new to Verilog. Is there any substitute for records in verilog?
I am working on converting a VHDL code which is heavy on records structures usage to verilog. It's a highly parameterized code using packages. I am also new to Verilog. Is there any substitute for records in verilog?