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VIP is the verified IP(it can be either testbench or RTL). Anyway you just need to integrate them to our testbench. Specification/documentation will be provided with every VIP which helps you to understand the usage of the same.
synthesizable VIP (or accelerated VIP as some vendors call it) are IPs that can be synthesized into emulators/FPGA to support verification. Advantage of using them is you can provide real time test stimulus to your synthesized design in FPAG/ASIC.
You can search accelerated VIP and you can find many examples of the same.
Hope this helps.
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