electronicman26
Full Member level 2
Hi
I want to simulate a simple resistor circuit in cadence, I have this veriloga code for resistor:
module simpleres(a, b);
inout a, b;
electrical a, b;
analog I(a,b) <+ V(a,b) / 1000;
endmodule
I am newbie, I start to doing this based on this manual: http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ICDesignVerilogA
in 3 step how I can transfer my code to the blank veriloga template?? (right click and pase dont work)
after transfer the code how I can save it?? (dont see any save botton)
what is the mean of this sentences: In ADE L, when simulating circuits that contain Verilog-A code, make sure to add "veriloga" (without quotes) to the stop view list. This can be accessed by going to Setup > Environment.
what should I do? where is setup??
I want to simulate a simple resistor circuit in cadence, I have this veriloga code for resistor:
module simpleres(a, b);
inout a, b;
electrical a, b;
analog I(a,b) <+ V(a,b) / 1000;
endmodule
I am newbie, I start to doing this based on this manual: http://venividiwiki.ee.virginia.edu/mediawiki/index.php/ICDesignVerilogA
in 3 step how I can transfer my code to the blank veriloga template?? (right click and pase dont work)
after transfer the code how I can save it?? (dont see any save botton)
what is the mean of this sentences: In ADE L, when simulating circuits that contain Verilog-A code, make sure to add "veriloga" (without quotes) to the stop view list. This can be accessed by going to Setup > Environment.
what should I do? where is setup??
