Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

[SOLVED] Simulating clock frequencies of a PLL - error due to rounding?

Status
Not open for further replies.

LatticeSemiconductor

Member level 2
Joined
Aug 31, 2013
Messages
45
Helped
0
Reputation
0
Reaction score
0
Trophy points
6
Activity points
589
Hi,

on my simulation i can observe a buffer overflow in my dual port fifo due to the writing bandwidth beeing 0.0223 % larger than the reading bandwidth. The writing clock is 6 times faster than the read clock, the write enabled for every 6th clock and the read always enabled.

The error is caused by the reference clock i set for the PLL, which is generating read and write clocks. The reference clock should be 55.6875 MHz, but in my testbench i can only specify clock periods in ps so i cannot set this exact frequency in the testbench.

How can i create such frequency for my testbench?

i read in a forum that one could use several time periods to obtain, in average, high and low time period of the desired frequency.

the problem is that i need the exact frequency for my fifo never to underflow or overflow. Is there a way to do that?

thanks
 

Are you doing a functional sim, or timing sim?
What is the timing resultion in the simulation? iirc, the default in modelsim is 100ps.

If its just a functional sim, why bother using "real" clocks at all? Just chop out the PLL and put in a simple clock generator model. If you know that the write clock will be 6 times the read clock, just make the write clock 10 ns and the read clock 60 ns. Then you can easily work out the number of clocks between two cursers on the simulation window.

If it's a timing sim, then just set the reference clock to be some number that doesnt require such accuracy
 
This is for a functional simulation. timing resolution was set to 'auto' on aldec simulator and i could change it to 1 fs. However, I'll go with the clock generator model since, like you said, i only care about frequency relations for every clock domain.

thanks
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top