Eligineer
Newbie level 3
Error in Vhdl Questa(10.b) Simulation: "No default binding for component at"
Hi,
I am an engineer who is fresh out of university and would love some help understanding what is wrong with the following code. For company security reasons, I am only including the relevant information. If something might be missing, please notify me and i will add it.
I have a module called "generator_top" that is used by the a different model "phc_top".
Below is the relevant instantiation for generator_top:
This module is then used in phc_top
where it is declared :
And mapped:
The following error appears upon simulation in the Questa simulator:
I have compared the two model instantiations and they are equal. Each individual code successfully compiles.
What could the issue be?
Thank you so much in advance,
-EJ
- - - Updated - - -
Figured out issue. I was compiling an older version of the file.
Thanks everybody
Hi,
I am an engineer who is fresh out of university and would love some help understanding what is wrong with the following code. For company security reasons, I am only including the relevant information. If something might be missing, please notify me and i will add it.
I have a module called "generator_top" that is used by the a different model "phc_top".
Below is the relevant instantiation for generator_top:
Code:
entity generator_top is
port
(
reset : in std_logic;
wait_interval : in std_logic_vector(31 downto 0);
comm_ref_clk : in std_logic; -- optical transmitter reference clk 100 MHz
ddr3_user_clk : in std_logic; -- ddr3 user clk 192 MHz
system_clk : in std_logic; -- system clk 64 MHz
-- phy interface:
tx_serial_data : out std_logic;
rx_serial_data : in std_logic;
-- registers interface:
debug : in std_logic; -- if debug = '1' then debug mode is active
selector : in std_logic; -- if selector = '0' ddr3 bus is selected, if selector = '1' simulator bus is selected
simul_mode : in std_logic_vector(1 downto 0); -- "00" -- simulator is not active, "01" -- simulator is active
crc_error_inject : in std_logic;
illegal_command_inject : in std_logic;
crc_err_cnt_rst : in std_logic;
illegal_command_cnt_rst : in std_logic;
crc_err_cnt : out std_logic_vector(15 downto 0);
illegal_command_cnt : out std_logic_vector(15 downto 0);
-- header parameters:
header_module_type : in std_logic_vector(15 downto 0);
header_reading_count : in std_logic_vector(31 downto 0);
header_module_number : in std_logic_vector(15 downto 0);
header_shot_counter : in std_logic_vector(15 downto 0);
header_stamp : in std_logic_vector(15 downto 0);
-- footer parameters:
footer_frame_counter : in std_logic_vector(31 downto 0);
footer_scan_num : in std_logic_vector(15 downto 0);
-- ddr3 buffer interface:
ddr3_fifo_wen : in std_logic;
ddr3_fifo_din : in std_logic_vector(31 downto 0);
ddr3_fifo_ready : in std_logic;
ddr3_fifo_empty : out std_logic;
ddr3_fifo_full : out std_logic;
-- user interface:
tx_clk_out : out std_logic; -- transmitter user clk 125 MHz
illegal_command_pulse : out std_logic;
crc_error_pulse : out std_logic;
crc_ok_pulse : out std_logic;
reading_ok_pulse : out std_logic;
reading_err_pulse : out std_logic;
led : out std_logic_vector(3 downto 0);
test_bus_out : out std_logic_vector(15 downto 0);--This is a probe to testthe hardware and has no other purpose.
sop_out : out std_logic;
eop_out : out std_logic;
insert_fake_packet : out std_logic;
reset_fifo : out std_logic;
-- tp:
transceiver_tp : out std_logic_vector(15 downto 0)
);
end generator_top;
architecture generator_top_arch of generator_top iswhere it is declared :
Code:
component generator_top
port
(
reset : in std_logic;
wait_interval : in std_logic_vector(31 downto 0);
comm_ref_clk : in std_logic; -- optical transmitter reference clk 100 MHz
ddr3_user_clk : in std_logic; -- ddr3 user clk 192 MHz
system_clk : in std_logic; -- system clk 64 MHz
-- phy interface:
tx_serial_data : out std_logic;
rx_serial_data : in std_logic;
-- registers interface:
debug : in std_logic; -- if debug = '1' then debug mode is active
selector : in std_logic; -- if selector = '0' ddr3 bus is selected, if selector = '1' simulator bus is selected
simul_mode : in std_logic_vector(1 downto 0); -- "00" -- simulator is not active, "01" -- simulator is active
crc_error_inject : in std_logic;
illegal_command_inject : in std_logic;
crc_err_cnt_rst : in std_logic;
illegal_command_cnt_rst : in std_logic;
crc_err_cnt : out std_logic_vector(15 downto 0);
illegal_command_cnt : out std_logic_vector(15 downto 0);
-- header parameters:
header_module_type : in std_logic_vector(15 downto 0);
header_reading_count : in std_logic_vector(31 downto 0);
header_module_number : in std_logic_vector(15 downto 0);
header_shot_counter : in std_logic_vector(15 downto 0);
header_stamp : in std_logic_vector(15 downto 0);
-- footer parameters:
footer_frame_counter : in std_logic_vector(31 downto 0);
footer_scan_num : in std_logic_vector(15 downto 0);
-- ddr3 buffer interface:
ddr3_fifo_wen : in std_logic;
ddr3_fifo_din : in std_logic_vector(31 downto 0);
ddr3_fifo_ready : in std_logic;
ddr3_fifo_empty : out std_logic;
ddr3_fifo_full : out std_logic;
-- user interface:
tx_clk_out : out std_logic; -- transmitter user clk 125 MHz
illegal_command_pulse : out std_logic;
crc_error_pulse : out std_logic;
crc_ok_pulse : out std_logic;
reading_ok_pulse : out std_logic;
reading_err_pulse : out std_logic;
led : out std_logic_vector(3 downto 0);
test_bus_out : out std_logic_vector(15 downto 0);--This is a probe to testthe hardware and has no other purpose.
sop_out : out std_logic;
eop_out : out std_logic;
insert_fake_packet : out std_logic;
reset_fifo : out std_logic;
-- tp:
transceiver_tp : out std_logic_vector(15 downto 0)
);
end component;And mapped:
Code:
comp_generator_top : generator_top
port map
(
reset => "not"(reset_n),
wait_interval => wait_interval_w,
comm_ref_clk => refclock, -- optical transmitter reference clk 100 MHz
ddr3_user_clk => tx_clk_out, -- ddr3 user clk 192 MHz
system_clk => tx_clk_out, -- system clk 64 MHz
-- phy interface:
tx_serial_data => tx_serial_data,
rx_serial_data => rx_serial_data,
-- registers interface:
debug => debug, -- if debug = '1' then debug mode is active
selector => selector, -- if selector = '0' ddr3 bus is selected, if selector = '1' simulator bus is selected
simul_mode => simul_mode, -- "00" -- simulator is not active, "01" -- simulator is active
crc_error_inject => crc_error_inject, -- will be done from registers block
illegal_command_inject => illegal_command_inject, -- will be done from registers block
crc_err_cnt_rst => crc_err_cnt_rst, -- will be done from registers block
illegal_command_cnt_rst => illegal_command_cnt_rst, -- will be done from registers block
crc_err_cnt => crc_err_cnt,
illegal_command_cnt => illegal_command_cnt,
-- header parameters:
header_module_type => header_module_type,
header_reading_count => header_reading_count,
header_module_number => header_module_number,
header_shot_counter => header_shot_counter,
header_stamp => header_stamp,
-- footer parameters:
footer_frame_counter => footer_frame_counter,
footer_scan_num => footer_scan_num,
-- ddr3 buffer interface:
ddr3_fifo_wen => ddr3_fifo_wen,
ddr3_fifo_din => ddr3_fifo_din,
ddr3_fifo_ready => ddr3_fifo_ready,
ddr3_fifo_empty => ddr3_fifo_empty,
ddr3_fifo_full => ddr3_fifo_full,
-- user interface:
tx_clk_out => tx_clk_out, -- transmitter user clk 125 MHz
illegal_command_pulse => open,
crc_error_pulse => open,
crc_ok_pulse => open,
reading_ok_pulse => open,
reading_err_pulse => open,
led => LED,
test_bus_out => test_bus_out_w, --This is a probe to testthe hardware and has no other purpose.
sop_out => sop_out,
eop_out => eop_out,
insert_fake_packet => insert_fake_packet,
reset_fifo => reset_fifo,
-- tp:
transceiver_tp => open
);
PHP:
)
# ** Error: (vsim-3732) ../../black_box_folder/alt/new/phc_ddr3_top.vhd(1138): No default binding for component at 'comp_generator_top'.
#
# (Port 'reset_fifo' is not on the entity.)
#
# Region: /phc_ddr3_top_tb/phc_ddr3_top_inst/comp_generator_top
# ** Error: (vsim-3732) ../../black_box_folder/alt/new/phc_ddr3_top.vhd(1138): No default binding for component at 'comp_generator_top'.
#
# (Port 'insert_fake_packet' is not on the entity.)
#
# Region: /phc_ddr3_top_tb/phc_ddr3_top_inst/comp_generator_top
# ** Error: (vsim-3732) ../../black_box_folder/alt/new/phc_ddr3_top.vhd(1138): No default binding for component at 'comp_generator_top'.
#
# (Port 'eop_out' is not on the entity.)
#
# Region: /phc_ddr3_top_tb/phc_ddr3_top_inst/comp_generator_top
# ** Error: (vsim-3732) ../../black_box_folder/alt/new/phc_ddr3_top.vhd(1138): No default binding for component at 'comp_generator_top'.
#
# (Port 'sop_out' is not on the entity.)
#
#What could the issue be?
Thank you so much in advance,
-EJ
- - - Updated - - -
Figured out issue. I was compiling an older version of the file.
Thanks everybody
