Kristya
Junior Member level 1
For a VCO alone, the jitter is accumulated as the time goes, but a PLL don't, is this right?
if right, then i want to know if a Frequency Locked Loop can null the jitter accumulation?
(FLL is something like PLL,and its input and output signals are frequency, so the transfor function for the inner VCO is Kvco ,not Kvco/s)
In a word, does jitter accumulaiton disapper in a close loop clock generation system?
Thank you for the help.
if right, then i want to know if a Frequency Locked Loop can null the jitter accumulation?
(FLL is something like PLL,and its input and output signals are frequency, so the transfor function for the inner VCO is Kvco ,not Kvco/s)
In a word, does jitter accumulaiton disapper in a close loop clock generation system?
Thank you for the help.
