inverter design by cadence to provide clock for transmission gate

Hi everyone
I want to design an inverter to provide clk and clkbar for transmission gate
I don not know how can I size my transistore?
does any body have an idea?
Thank you

Saraadib said:

Hi everyone
I want to design an inverter to provide clk and clkbar for transmission gate
I don not know how can I size my transistore?
does any body have an idea?
Thank you

Click to expand...

Hello,

here you can find a good lecture notes from Berkeley university about inverter sizing.

**broken link removed**

Kindest Regards

The size will fall out of optimization for whatever it is
that you care about. We do not know what that is.
Maybe you care about propagation delay, or not.
Maybe you care about clock feedthrough or charge
injection. Maybe you only care about minimum layout
area.

Transistors have properties, you fiddle them around
until you understand, then until you like the result.

Unless you're in some kind of environment where the
real goal is to demonstrate mathematical approaches.

dick_freebird said:

The size will fall out of optimization for whatever it is
that you care about. We do not know what
that is.
Maybe you care about propagation delay, or not.
Maybe you care about clock feedthrough or charge
injection. Maybe you only care about minimum layout
area.

Transistors have properties, you fiddle them around
until you understand, then until you like the result.

Unless you're in some kind of environment where the
real goal is to demonstrate mathematical approaches.

Click to expand...

I need inverter to provide clk bar for transmission gate,as you know transmission gate is consist of nmos and pmos in parralel with clk and clk bar at the gate of nmos and pmos respectively ,So I need to design inverter to provide that clk bar ,this is my goal ,
But I do not know how I have to choose inverter size ?

You need to see how different sizings affect the primary
and secondary attributes I mention, and pick what does
best for your priorities.

For example, a very fast / hard-driven tgate will put
larger charge pulses onto input and output which might
be unsuitable for a sample / hold application or an ADC
input where glitch energy might end up in the data.

If your N switch and your P switch are differently
sized then their drive might be as well, and again this
might differ in turn by whether you care more about
raw speed or about clean quiet switch transitions.

Choose your size by setting up simulation test
benches that exercise the "care-abouts" and run
the same core circuit with Nwidth and Pwidth
parametric analysis, identify the relation of these
to each performance param, and in the end pick
your sweet spot overall (or by priority).

dick_freebird said:

The size will fall out of optimization for whatever it is
that you care about. We do not know what that is.
Maybe you care about propagation delay, or not.
Maybe you care about clock feedthrough or charge
injection. Maybe you only care about minimum layout
area.

Transistors have properties, you fiddle them around
until you understand, then until you like the result.

Unless you're in some kind of environment where the
real goal is to demonstrate mathematical approaches.

Click to expand...

dcv said:

Hello,

here you can find a good lecture notes from Berkeley university about inverter sizing.

**broken link removed**

Kindest Regards

Click to expand...

dick_freebird said:

You need to see how different sizings affect the primary
and secondary attributes I mention, and pick what does
best for your priorities.

For example, a very fast / hard-driven tgate will put
larger charge pulses onto input and output which might
be unsuitable for a sample / hold application or an ADC
input where glitch energy might end up in the data.

If your N switch and your P switch are differently
sized then their drive might be as well, and again this
might differ in turn by whether you care more about
raw speed or about clean quiet switch transitions.

Choose your size by setting up simulation test
benches that exercise the "care-abouts" and run
the same core circuit with Nwidth and Pwidth
parametric analysis, identify the relation of these
to each performance param, and in the end pick
your sweet spot overall (or by priority).

Click to expand...

Actually I am desiginig N path filter which is consist of an ideal switch ,resistors and capacitor ,now I want to replace this ideal switch with real switch ,I know that I can use nmos ,pmos or transmission gate as switch ,in transmission gate nmos and pmos gate are connected to clck and clkbar ,that is why I need inverter to provide clck bar ,but the problem is for inverter size I do not know what should I care about? And what is my priority

You should care about the load that you will drive and the frequency you need.

You need to have a short propagation delay in respect to your clock signal period. If you read the slides I posted you, you will see that the delay mainly depends on the load(in your case the load is represented by the cap seen on your transmission gate), the voltage swing of your signal( ex 0 - 3.3 V --> Vswing = 3.3V) and the current you will provide to your inverter I0.

The ratio between I0 and Cload will provide you the maximal hypothetical Slew Rate (SR = I0 / Cload).

Supposing that:

Cload = 1pF
f_clk_max = 1 MHz --> period_clk_min = 1 us

in order to ensure your clock will propagate in time the propagation delay has to be lower than the half of period_clk_min. Assuming that the delay is a tenth of the period_clk_min (to be sure):

delay_max = period_clk_min /10 = 100 ns

By the formula is known that the delay is:

delay_max = (V_clk_swing / 2) / SR = (Cload * V_clk_swing) / (2*I0)

where: V_clk_swing is the voltage swing of your clock signal(generally 3.3 volts in standard tech)
SR = Slew Rate = I0 / Cload
Cload = load capacitance seen at the output of the inverter
I0 = current passing trough the inverter

knowing now the maximum delay, delay_max, you can extrapolate the current I0 you need for your inverter by the previous formula:

I0 = (Cload * V_clk_swing) / (2*delay_max)

Knowing now the current you can calculate the size of the transistors.

By Ohm's law: V = R*I --> Vds = Ron * I0

Ron = Vds / I0

In inverters, in order to obtain the minimum delay propagation(max speed), you have to work in the linear(triode) region. The formula of sizing a transistor in linear region to obtain a certain Resistance Ron, is given by:

Ron = L / (K * W * (Vgs - Vth))

Where K= u * Cox

Here you can find more about linear region, and how to properly size:
**broken link removed**