maxy_spy
Newbie level 6
Hello ,
I want to know that how does one define the basic specs for characterization of a new library on a new technology node where no .lib is present.
for example: if we have a library that does not come with an existing .lib then as a characterization guy how do I come up with the Min, Max slew and Min,Max load ranges?
Do I have to do some schematic level simulations to come up with the numbers?
I read a thesis reference:
https://shareok.org/bitstream/handle/11244/10182/Anne_okstate_0664M_11266.pdf?sequence=1
Min slew:
on Page 38 he shows that the Min slew is less than the delay of the cell.
So, is the min slew derived from connecting the biggest cell in the library ( drive strength wise), providing the ideal signal at the input, looking at the o/p slew of the 2nd statge and using that as a min slew for the whole library because it will be the fastest delay?
Max slew: is the same method used as above but with the smallest cell in the library?
Min load: Is The load is determined using the minimum sized inverter (INVX1) of the cell library?
from page 11 of the same thesis i found this
PMOS_VTL W=0.5e-06 L=0.05e-06
NMOS_VTL W=0.25e-06 L=0.05e-06
Coxforthisprocess=26.67fF/um2 (obtainedfromsimulation)
and then with the formula he derives C = 1fF
Max load: I know that the tool will derive the max load value based on the max_transition value
the max_transition value in the setup right now is 0.90xmax_slew (default from the tool) but I am not sure that this will still hold true for 65nm or less than that nodes. How do i come up with this value?
Right now, I have been used this attributes from the previously characterized .libs and I have to come up with the specs and ways to characterize this.
It will be a great help to me if you can answer these questions for me.
thank you
I want to know that how does one define the basic specs for characterization of a new library on a new technology node where no .lib is present.
for example: if we have a library that does not come with an existing .lib then as a characterization guy how do I come up with the Min, Max slew and Min,Max load ranges?
Do I have to do some schematic level simulations to come up with the numbers?
I read a thesis reference:
https://shareok.org/bitstream/handle/11244/10182/Anne_okstate_0664M_11266.pdf?sequence=1
Min slew:
on Page 38 he shows that the Min slew is less than the delay of the cell.
So, is the min slew derived from connecting the biggest cell in the library ( drive strength wise), providing the ideal signal at the input, looking at the o/p slew of the 2nd statge and using that as a min slew for the whole library because it will be the fastest delay?
Max slew: is the same method used as above but with the smallest cell in the library?
Min load: Is The load is determined using the minimum sized inverter (INVX1) of the cell library?
from page 11 of the same thesis i found this
PMOS_VTL W=0.5e-06 L=0.05e-06
NMOS_VTL W=0.25e-06 L=0.05e-06
Coxforthisprocess=26.67fF/um2 (obtainedfromsimulation)
and then with the formula he derives C = 1fF
Max load: I know that the tool will derive the max load value based on the max_transition value
the max_transition value in the setup right now is 0.90xmax_slew (default from the tool) but I am not sure that this will still hold true for 65nm or less than that nodes. How do i come up with this value?
Right now, I have been used this attributes from the previously characterized .libs and I have to come up with the specs and ways to characterize this.
It will be a great help to me if you can answer these questions for me.
thank you
