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Value of Insertion delay and skew

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manoj.ec

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Setup and Hold violation depends on the "value of the clock skew".

Since clock skew is the difference of insertion delay of two flops (launch and capture flops),
Can the insertion delay be any value?
Can it be greater than clock period?

On what basis the insertion delay value is set?
 

My thought is below:
- Basically, launch and capture flops are in same domain, they should have the same value of clock latency with all flops in their clock domain.

- You can make it any delay value if you maintain below:
+ Timing is MET for that path and other paths related to those flops.
+ Latency is short enough to guarantee the switching power on clock line.

- And sure, it can be longer than clock period. In fact, it should be as short as possible.
 

manoj.ec said:
Can the insertion delay be any value?
Click to expand...
yes, it's dependent on the depth of the clock tree that was synthesized, more FFs in the design the bigger the tree and hence the more insertion delay.

manoj.ec said:
Can it be greater than clock period?
Click to expand...
see the comment above, if the tree is large enough it will result in an insertion delay that is larger than the clock period, hence the reason some designs require a PLL.

manoj.ec said:
On what basis the insertion delay value is set?
Click to expand...
read the points made above.
 

my thought is insertion delay is depended on size of the block.
 

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