Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Concepts of Synchronization

Status
Not open for further replies.
A

aravind9

Newbie level 5
Joined
Sep 22, 2013
Messages
8
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,344
1. How to overcome the convergence and Divergence in the crossover path?

2. What is the difference between Dual Port RAM Synchronizer and Asynchronous FIFO Synchronizer?

3. Why the Dual Port RAM is having less area when compared with the FIFO memory?
 

1.Convergence-> Feed a synchronizer only from a flip flop and not from combi logic.
Divergence -> Synchronize a signal only once from 1 clock domain to another. Don't generate multiple copies.

2. What is a dual port RAM synchronizer? Never heard of it before...

3. A FIFO internally has a RAM along with other logic..So RAM area should always be less...
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top