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How to calculate Latency of a PID block designed in VHDL

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areebaa

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Hi,
i have designed simple PID Controller in VHDL and synthesized to be used in cadence. How can i calculate the latency if the clock is 10MHz. this has of course inputs and outputs.
Thanks you
 

1) How are you defining latency?
2) It has inputs AND outputs? wow.
3) I would just simulate it and see what comes out.
 

sorry for short intro. Now i have attached image. Actually i have series of blocks and in the begining mux is used to multplex the two inputs and and the other side demux is used to receive the processed Ai , Bi in separate time. i mean propogation time from input to output. actually i want to synchronize the inputs and outputs by estimatiing delays in the sub-blocks. how can i guarentee that Ai is processed and availabe at Ao at t1 and similarly Bi is processed and availabe at Bo at t2 (next cycle) synch_dgitalpath.PNG
barry said:
1) How are you defining latency?
2) It has inputs AND outputs? wow.
3) I would just simulate it and see what comes out.
Click to expand...
 

A digital filter wil also require a clock, so there will always be some latency
 

Hi,

You may simulate this.
Input is a step response....Then wait until you see the desired output level..

In reality the input to output delay should be known by design.
Usually this delay should be less than the analog anti aliasing filter of the ADC, and the reconstruction filter of the DAC.

But if you want to use the "latency time" to calculate loop stability, this will fail, because the PID control acts like a filter and the group delay of the filter may be way more than the sum of all the other delay times before..

Klaus
 

The mux scheme doesn't make much sense as shown. A PID or digital filter in general involves internal memory that must be unique for each channel. So if you implement multiplexing, it must act inside the digital filter, too.

Apart from this point, you get the digital signal processing latency by counting the pipeline stages.

There are however two kinds of characteristic time parameters
- the latency of pipelined design, given by the number of register levels along the signal path
- the group delay (and also the settling time) of a time discrete filter according to it's order

Usually, the sample rate of digital filter is only a fraction of the system clock, the above parameters differ by a respective factor.
 

****
how can i guarentee that Ai is processed and availabe at Ao at t1 and similarly Bi is processed and availabe at Bo at t2 (next cycle)
Click to expand...
You can guarantee this by design. Usually some kind of state machine inside your FPGA/ASIC controls this timing.

Signal processing in an FPGA usually is a synchronous real time task with a fixed relationship between the channels. Therefore it usually is impossible that the timing between the channels vary.

Klaus
 

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