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[SOLVED] Verilog- Inside case statement, bit-selected regs w/reduction operator doesnt work

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Valerius

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Hi everyone,

I am designing a FSM machine that controls speed configurations of my step motor. It is ALMOST done, however this bug gave me no other choice but posting it here.

I can provide more code if wanted.

Code: 
                       //Speed indexes
	               parameter  _40 = 11,
				  _20 = 10,
				  _10 = 01,
				  _0 = 00;

Code: 
              //Speed Adjustment
	      always @(posedge Clk)
		case(Speed)
			_40: DONE <= &counter[18:0];
			_20: DONE <= &counter[19:0]; // <------ THIS ONE DOES NOT WORK PROPERLY
			_10: DONE <= &counter;
			_0:  DONE <= 1'b0;
			default: DONE <= &counter[18:0]; //Default speed is 40 step/second				
		endcase


Speed is a 2-bit input pin that holds the values: 00, 01, 10, 11, DONE is a simple wire and counter is 21 bit register that counts one by one, however even though my _40, _10 and _0 options work, strangely _20 one doesn't it just keeps being low.

I use the same code in my testbench for all of the cases, yet, the one with _20 is still giving me false results.

Thanks!

- - - Updated - - -

CORRECTION: _20 gives the same result as the _40 !!!!
 

CORRECTION: _20 gives the same result as the _40 !!!!
Click to expand...
Did you notice that 10 and 11 are decimal rather than binary literals? So the case stament will hardly work as expected for a two bit vector Speed.

And please post meaningful code parts instead of snippets.
 

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