[SOLVED] Maximum collector-emitter voltage of a transistor in AC regime.

Hello there,

This might be a quite basic question, but I am maybe missunderstanding something. What is the maximum collector-emitter voltage that a transistor can hold when operating as a normal amplifier? In other words, how high are the AC signal between the collector and emitter allowed to swing and how is this related to BVCEO? If my transistors have a BVCEO of 1.5 and I observe a time domain signal that swings up to 1.8 V with a quiescent VCE point of 1 V, how dangerous is this for it? I assume it has a relation with the frequency of the signal because it determines how much time (power) the transistor remains over the 1.5 V scale, but I cannot get the full picture stil how to relate those 2 maximum voltages.

Would appreciate any comment or explanation about this. I wouldn't like to blow up my circuit.

Many thanks and best regards.

Megaknaller

Never came across a BJT with BVCEO of 1.5V. What kind of devices are you asking about?

Generally, BJT don't tolerate avalanche breakdown. Pemanent damage can be expected.

BICMOS BJTs in process nodes < 90 nm might have such BVCE0 .

Using low-ohmic base control, or an appropriate resistance between base and emitter allows you to go up to BVCB0, which might be a (little) bit higher.

Yes, 220 nm or below SiGe/CMOS processes exhibit typical values for BVCEO around that. I infered too that if the basis resistance is relatively low, the transistor could swing over BVCEO without blowing up (at least during a test phase) but I suppose it would also have a long term impact on its expected reliability. This is not an issue for me now, but would be great if someone can point out some info about the relationship between BVCEO and the maximum allowed swing before the transistor fails because of avalanche breakdown or any high current effects.

Thank you for your replies guys,

Megaknaller

how high are the AC signal between the collector and emitter allowed to swing

Click to expand...

As a general rule this is done by turning the transistor almost on and almost off. The volt levels you get depend on what components are in the collector and emitter legs.

Say you have a 10 ohm resistor in the collector leg only. You can obtain maximum AC voltage swing by driving the transistor so its average internal resistance is 10 ohms. Thus it will have a DC component of VCC/2 at the collector pin.

To get the full range of transistor operation, you generally apply a bias voltage from 0.3V to 0.7V (relative to emitter). However we normally think in terms of applying bias >>current<<, because (a) its response is more linear, (b) it is easier to measure, and (c) it is easier to adjust.

Hi Brad, and thanks for the reply.

While the statement is right in order to avoid the saturation region in a transistor, nevertheless there are cases, like mine, where the transistor bias point is biased at one VCE, and from that point it swings up and down with such an amplitude that it does not enter the saturation region but it does overpass the maximum BVCEO of the device, say, i have a BVCEO of 1.5, a saturation voltage of 150 mV and my transistor is biased at 1 V with a 700 mV swing. It works all the time in the active region but it surpass the maximum stated BVCEO. This behaviour is common in typical advanced SiGe or BiCMOS processes.

The question is then how high is this surpass allowed to be. The ultimate value should be limited by the down level at the transistor saturation voltage, but that does not necessarily means that the transistor will hold all the way up to that swing without degradating or in worst case blowing up because of destructive avalanche effects. I guess that, as long as the impedance at the transistor basis is not an poen circuit, this value will be somewhere between BVCES and BVCEO, being BVCES typically 3 to 4 times higher than BVCEO.

Hope I could made the formulation better and maybe someone can share experience or some interesting documents related to this topic.

Is your transistor a darlington? That would explain its 1.5V bias voltage.

When we use a transistor as an amplifier, we often want linear response besides maximum voltage swing. The problem is that we lose linear response near full-On and full-Off. Therefore we must choose a tradeoff in regard to how much we can get out of the transistor.

As for how to detect when it is biased to saturation, the definition is (I think) the point where C-E current stops increasing as we increase bias. The concept is easy to grasp. However to measure it is not necessarily easy to do experimentally, because there are transistors which will overheat before reaching saturation (I think). Overheating can ruin a transistor's operating characteristics.

We might install resistors at all legs, for safety to the transistor, but soon we find ourselves going to a lot of trouble just to measure one transistor's saturation point.

There is also a question how much bias current a transistor can tolerate. I would be wondering which will occur first, the bias junction saturating, or, being destroyed? Because I hate to destroy components.

BVceo is a pretty useless number. It embodies barely-
controlled amplification of highly variable leakage against
an arbitrary current. And it bears no relation to any useful
circuit (open-base BJT being good for pretty much nothing).

BVcer (your R) is what you'd like. Since this is an RF device
I'd bet BVces is closer to normal (50 ohms or maybe a couple
of hundred, tops). BVcbo ought to run close to BVces.

But what you don't get to know, without some digging, is
what the reliability impact of high collector voltage is. Odds
are, not much until you start avalanching and throwing hot
carriers at the base-adjacent oxide. I've seen BJTs subjected
to repetitive avalanche with negligible walk on any params.
But you can't say that will be your outcome, especially since
this device is not developed for ruggedness but maximum
sportiness, and rated likewise.

One thing you might be interested in, is what the current
vs voltage profile is as you approach and exceed rated
breakdown. Many bipolar models have no good emulation
of active breakdown behavior, and modeling folks, they
don't care to model outside-ratings attributes if they can
avoid it.

I'd be trying to extract insight from the foundry's reliability
folks. But you're liable to just get a pat on the head and be
told to be a good boy.

Meanwhile ST offers High-speed, medium-voltage and high-voltage SiGe HBTs with Ft ranging from 320 GHz to 65 GHz
associated to BVceo between 1.5 V and 3.2 V .

Thanks for the replies guys, the transistor is not a darlington. It is a typical SiGe HBT within a process which offers ft of about 350 GHz, I mean, I guess it is not a typical component that can be took off the shelf for RF design. The technology guys haven't provide any satisfactory answer by now but instead as Freebird recommended, indicated it is highly recommended to not surpass the values provided in the documentation. Problem is, at some designs I have the BVCEO like above the limit for about 200, 300 mV at most. I assume nothing can happen, first because I don't have any real open at the basis and second and most important because I am not gonna operate the circuit over a long time. It is basically for test purposes.

I will try to get more info from these guys but atm it seems it's almost a dead end . Thank you all for your contributions.

Regards,

MK

Do you have more than one sample?

If so, take one and "drive it like you stole it". Then you
will find the limits and know where to back off for longer
term testing.