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[SOLVED] Clocking wizard - can not generate a divided clock which slower than 6.xx Mhz ?

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slutarius

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I am using Kintex7 with Vivado 2014.4.
I want to have a divided by 8 clock using clocking wizard ( MMCM, PLL ) from input 33Mhz clock.
Vivado keeps saying I can not generated a clock slower than 6.xx Mhz ( xx is a number which I can not remember now ).

What is the point here ?

Do I need to use another method ?

- - - Updated - - -

I just found the point, maybe it can help to solve my issue:

When CLKOUT4_CASCADE = TRUE, MMCM_F
OUTMIN
is 0.036 MHz

Seri7 datasheet.
 

The problem stems from the VCO frequency, the PLL/MMCM has to multiply the clock up to the VCO frequency range and then divides it down again. So to get it up to VCO input range means you can't divide it down enough to give you the frequency you want (33/8) MHz.

The other method is use only the 33 MHz clock in your design and just make a divide by 8 counter generating an enable pulse every eight clocks. And write all the code for the 33/8 MHz clock as clock enabled FFs.
 

ads-ee said:
The problem stems from the VCO frequency, the PLL/MMCM has to multiply the clock up to the VCO frequency range and then divides it down again. So to get it up to VCO input range means you can't divide it down enough to give you the frequency you want (33/8) MHz.

The other method is use only the 33 MHz clock in your design and just make a divide by 8 counter generating an enable pulse every eight clocks. And write all the code for the 33/8 MHz clock as clock enabled FFs.
Click to expand...

So what does this attribute mean ?
When CLKOUT4_CASCADE = TRUE, MMCM_F OUTMIN is 0.036 MHz

My thought is CLK 4 of MMCM would have this MINIMUM freq. Is that correct ?
 

Interesting never looked at this CLKOUT4_CASCADE attribute, but it does look like it should give you what you are looking for as it gives you a maximum division of 16384. Though it looks like the tools depending on the version may or may not have been fixed according to AR #56180.
 
I am using 2014.4 which is newer on the AR. If I switch the CLKOUT4 Cascade ON, still limitation is 4.69.. Mhz. It means no help.

Talking about VCO range, even I set MUL and DIV parameter to meet the VCO range on datasheet, it still says that VCO range is not correct from MUL and DIV params. Quite confused about this kind of feature still.
 

Looks like they haven't fixed the AR yet, though the AR does suggest you can ignore the violation.
 

I enabled the CLKOUT4_CASCADE attribute and can not make the 4.125 output clock from MMCM. Even select CLKOUT4 output or others.

clk_in1 = 33.33Mhz
MUL = 20
DIV = 1
VCO 666.6Mhz

CLKOUT0 div = 20
CLKOUT1 div = 80
CLKOUT2 = CLKOUT3 = CLKOUT4 = 160 ( all failed )

I could see the info on Port renaming is followed what I want. But when I hit OK, it say Error.

edab.png
edab2.png
edab3.png
 

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Tried with 2015.1 and it appears AR#56180 hasn't been fixed yet.
 
Thanks. I am going on with clock divider by Flops to make 4.125Mhz. MMCM plays with 33.33Mhz and 8.25Mhz.
 

you could also instantiate the component for the MMCM directly. You don't need to use the ip-integrator if it doesn't currently work.
 
vGoodtimes said:
you could also instantiate the component for the MMCM directly. You don't need to use the ip-integrator if it doesn't currently work.
Click to expand...

Thanks. But I think there should be a benefit to use ips, right ?
 

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