matching in layout design and hot n well

matching in layout design

Can anyone pls explain me in a simple gist what is matching in layout design. I used a current mirror and i didnt match the L and W the same for 1 transistor and the other 2 were the same of the total 3 current mirror structure. The reason i did was when i matched them equally the current got copied more that what i was giving also i the circuit to which i was feeding the copied current provided the required results when i tuned this current mirror bu changing the L and W. After all isnt the ultimate aim to copy the current required. Isn't that what current mirrors are used for. But though the result was good my design needed improvement in matching part. so what is matching and why is it important. So is matching more important always than the desired performance results??? And i also got to know matching is not just making the L and W same. I was told something like aspect ratios of this block (having some transistors) is dependent on the other block (with other transistors). can someone pls explain.Thank you!!!

hot n well in layout design

Hi can anyone pls explain to me what is hot n well layer and what is it used for?? Meaning i had an error when i the source potential of my pmos was larger than the bulk potential thereby current flowing from source to the substrate. After i used hot n well on top of the nwell surrounding the pmos the error was cleared.

Pls check this link. for the above mentioned error i found the solution here
https://iccustomlayout.blogspot.ca/
I found "PMOS in the N-well should be surrounded with P-diffusion guard ring.
P-diffusion guard ring should be tied to ground. P-diffusions from the
PMOS inject stray holes into the N-well. These stray holes could be
collected efficiently by the P-diffusion guard ring that is biased to ground to attract the holes."

So i can understand using guard ring the stray holes are pulled to ground. This concept is clear. So similar to this can anyone explain how the current flows when using a hot n-well that helps in clearing the error...
In simple terms pls.. Thanks in advance!!!

I believe you are suppose to put the p+ diffusion guard ring around the nwell and not around the pmos inside the nwell. Keep in mind that if the source potential is > than the bulk you risk turning on the parasitic VPNP. The p+ diffusion guard ring around the nwell will act as the VPNP collector.