mepriyasingh
Member level 2
how we finalize synthesis, which report should we check and which should be clean in what sence.
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After synthesis, you can check:
- Clock ideal STA. Knowing critical parts about timing in you design functional mode.
- Area ( Without clock cells and optimization cell from PnR ). Inform it to PnR members would be helpful for them.
- SDC quality. ( report by check timing and so on .. )
If you want, you can check power report, but it is not closed to final number because lacking of clock cells and optimization cells.
There is no report says "OK to release". You need to clarify what is your target of synthesis.
Basically, synthesis need to clean "0" clock latency timing and Formal verification. The rest of thing like cell counts, static power ... are not so important as this phase, but it is depended on your targets before doing synthesis.