mark_nctu
Advanced Member level 4
ldnmos
My IC uses a open drain LDNMOS for output. The Vout.max is 20V and
core circuit is 5V system. The ESD testing was fail when OUT-VCC+ and
OUT-VSS+ zapped (only 500V). How to improve ESD ?
Thanks
My IC uses a open drain LDNMOS for output. The Vout.max is 20V and
core circuit is 5V system. The ESD testing was fail when OUT-VCC+ and
OUT-VSS+ zapped (only 500V). How to improve ESD ?
Thanks