zhangljz
Member level 5
Hi,
I am using RTL compiler for synthsise, and I want to implement clock gating. I don't have ICG cell, so I wrote a module as the clock-gating module, which has "ck, D,Q,enable, test", where test is the clock gating control signal.
The question is that I want to connect pin 'test ' of all the ICG instances together to a port 'CG_test'. How can I do this in RTL compiler?
Thank you
I am using RTL compiler for synthsise, and I want to implement clock gating. I don't have ICG cell, so I wrote a module as the clock-gating module, which has "ck, D,Q,enable, test", where test is the clock gating control signal.
Code Verilog - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 module ICG_posedge ( input ck_in, enable ,test, output ck_out ); reg en1; wire tm_out, ck_inb; assign tm_out = enable | test; assign ck_inb = ~ck_in; always @(ck_inb, tm_out) if(ck_inb) en1 = tm_out; assign ck_out = ck_in & en1; endmodule;
The question is that I want to connect pin 'test ' of all the ICG instances together to a port 'CG_test'. How can I do this in RTL compiler?
Thank you
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