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Validity of the output signal in a Digital Design

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aravind9

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How to ensure the validity of the output in a design by a signal? How exactly the validity concept works?
For example: In a design after so many clock pulses the output settles to a final value and how can we say that is stable and valid output signal for the given input?
 

The easiest way is to generate a separate output signal that is active only when the output is valid.

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Something like this:
Code: 
         __    __    __    __    __    __    __    __    __ 
clock __|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |__|  |
                ___________ _____ _____
idata XXXXXXXXXX___________X_____X_____XXXXXXXXXXXXXXXXXXXXX
                            ___________ _____ _____
odata XXXXXXXXXXXXXXXXXXXXXX___________X_____X_____XXXXXXXXX
                            _______________________
valid _____________________|                       |________
 

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