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Methods to fix timing violations in synthesis stage

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biju4u90

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While synthesizing an OR1200 SoC in Cadence RTL compiler, I got a worst slack of the order of -1000 ps in reg to reg path. Can I proceed to the PnR stage with this timing value so that I can fix them in PnR stage?? What are the possible methods available to fix this violations or reduce these violations in synthesis stage??
 

Hi

I think you can minimize and go ahead.Because these violations are effective only once real clock tree is synthesized.so you can proceed.

To my idea placement aware synthesis is done,in the synthesis stage.
 

cyrax747 said:
I think you can minimize and go ahead.
Click to expand...

Can you please suggest some methods to minimize the worst negative slack??
Changing the effort level to high may be one method I think. Any suggestions for other methods?
 

I know in dc compiler we use compile -ultra,but i dnt have any idea of rtl compiler,which option we use.
 

Can you please brief out what is the difference between compile command and compile -ultra command in dc compiler so that I can search for an equivalent command in RTL compiler??
 

Hi

Long back i have worked on it.ultra option is efficient than regular compile command.give ur email id, i can send user manual if i have it.
 

did u try debugging the timing report as to why the slack of 1000ps?
I would start there rather trying any options first
 

I can only answer it at a very top- (concept-) level.

In order to reduce the negative slack, try to reduce the combinational logic between two the two registers (flip-flops). Or adding a pipeline can also be a solution.

If your design is big, try out 'incremental compilation' to achieve timing closure for a particular partition that does not meet timing requirements, while preserving the compilation results for partitions that have met design requirements.
 

Guys - Can I ask whether it's a Setup Slack or Hold Slack ?
 

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