Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Difference between the two cases of the designing a inverter

Status
Not open for further replies.

asicpark

Member level 1
Joined
May 14, 2004
Messages
35
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
273
Hi all,

I have a basic question I have been had for a long time.
For designing the inverter, there are two ways to sat the output
to the middle of the supply, assuming Un=2Up.

Case1 : (adjust the witdh) Pmos : 2W/L, Nmos : W/L
Case2 : (adjust the length)Pmos : W/L, Nmos : W/2L

Actually, I don't know what difference is, or benefits and drawbacks.
Does anyone who knows about this?

Thanks,
 

Re: Difference between the two cases of the designing a inve

For digital design we use the minimum length for both PMOS and NMOS because we wont care about the output resistance of the MOSFET in the saturation region.
 

In theory, both case is same. But, longer transistor length means longer switching time. Usually, keep the same length.
 

Re: Difference between the two cases of the designing a inve

Case 1 should be choosen. In digital circuit, the minimum L is choosen, and the channel length modulation can be igonerd, since it just a switching circuit.


regards,
smart
 

Re: Difference between the two cases of the designing a inve

* first the "switching" as mentioned in the first post above.

* second: in order to minimize you will chosse the CD (critical dimension = min. allowd length) for all types of digital most. So you choose e.g. l=0.13
The width of nmos will be as fast as you need!
And for pmos the same (in case that you don't need symetry of rise and fall time) or 2-3 times wnmos.
 

Re: Difference between the two cases of the designing a inve

both inverters have the same input caps while the first type has much bigger drivering capability; secondly, not sure your model can support 2*L; thirdly, it's not good for matching; but larger L usually means you have much smaller leakage current, but in these cases, your NMOS gate leakage also increases.
 

Re: Difference between the two cases of the designing a inve

It is not the design task to have the Vth of the inverter in the middle of the supply voltage. The prior task is to guarantee symetric rise and fall times. So the dynamic is of more interst than the static case.

A symetric static (dc) transferfunction differs from symetric rise and fall times since there are different input caps to load for p and n most
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top