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[VHDL] How to do forwardtrace/backtrace in VHDL?

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maulin sheth

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Hello ALl,

Can any one help to understand of how to do forward trace / back trace in the VHDL RTL coding. In which RTL is containing Entity, Architecture and Configuration (with for loop for instantiation)

Thanks a lot in advance.

--
Thanks & Regards,
Maulin Sheth
 

What do you mean by forward trace / back trace ?
 

maulin sheth said:
Can any one help to understand of how to do forward trace / back trace in the VHDL RTL coding.
Click to expand...
What is that?

As a general guideline, I can suggest you to refer to the design spec. which might might contain an architectural block diagram or a state diagram! After that try to follow the RTL.
 

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