NeginMadani
Newbie level 2
I would really appreciate your help. I wrote the following testbench code to test my 6th order FIR filter. It worked perfectly for my behavioral code, but when I try to use it after synthesis for my structural gate-level netlist, I get this error:
ERROR:HDLCompiler:1728 - "/home/..." Line 24: Type error near xin ; current type signed; expected type signed
ERROR:HDLCompiler:1728 - "/home/..." Line 25: Type error near yout ; current type signed; expected type signed
ERROR:HDLCompiler:854 - "/home/..." Line 12: Unit <behavior> ignored due to previous errors.
VHDL file /home/... ignored due to errors
Code VHDL - [expand] 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; ENTITY test_six_order_fir_filter IS END test_six_order_fir_filter; ARCHITECTURE behavior OF test_six_order_fir_filter IS signal clk : std_logic := '0'; signal xin : signed(7 downto 0) := (others => '0'); signal yout : signed(15 downto 0) := (others => '0'); constant clk_period : time := 10 ns; BEGIN -- instantiate the Unit Under Test (UUT) uut: entity work.six_order_fir_filter PORT MAP ( clk => clk, xin => xin, -- Line 24 yout => yout -- Line 25 ); -- clock process definitions clk_process :process begin Clk <= '0'; wait for clk_period/2; clk <= '1'; wait for clk_period/2; end process; -- stimulus process, using various values as inputs to observe the output. The input value changes after 1 clock period = 10ns. stim_proc: process begin wait for clk_period*2; xin <= to_signed(-4,8); wait for 1*clk_period; xin <= to_signed(2,8); wait for 1*clk_period; xin <= to_signed(0,8); wait for 1*clk_period; xin <= to_signed(-2,8); wait for 1*clk_period; xin <= to_signed(5,8); wait for 1*clk_period; xin <= to_signed(4,8); wait for 1*clk_period; xin <= to_signed(-5,8); wait for 1*clk_period; xin <= to_signed(6,8); wait for 1*clk_period; xin <= to_signed(10,8); wait for 1*clk_period; xin <= to_signed(0,8); wait; end process;