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Two submodule with the same clock period, but with different root clock

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In some designs, I notice that they have the same clock period, and with the same clock source ( PLL, for example ), but some submodules in this design use "different clock", which means that the source clock drives different clock root for these submodules, and makes the communication between submodules asynchronize.

It makes me confuse...Why do we have to do this?

Thanks.
 

keep in mind to check the phase of the two clocks.
 

One requirement could be to go easy on the clock tree.

By making the two clocks asynchronous you are telling the CTS tool that these clocks needn't be balanced, that means the skew can be different for the two clocks. So when doing CTS, the tool will not insert additional buffers to balance the two clocks. This saves area and gives more freedom to the tool to meet the timing for more critical paths.

This is mostly the case when you have modules running using same clock source but has very little communication between them.
 
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