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how to generate all the mismatching warning in Modelsim and RTL compiler

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zhangljz

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Hi,

I have a problem with modelsim and RTL compiler that not all the possible warning is generated. For example when I simulate and synthesize this code:

module a_test (
input [5:0] in_a,
input [3:0] in_b,
output c

);

assign c = ( in_a==in_b)? 1 : 0;

endmodule

Then the tools will treat it as (in_a == {2'b0, in_b}) ? 1 : 0

But, what I want is to generate warning for all the mismatching connection or comparison etc, so we know where there are this kind of mismatching and we can decide which are acceptable and which are bugs.

Anybody knows?

Thanks.
 

you can use assertions to warn for mismatch sizes.
 

Hi aruipksni,

I read some materials and it seems that assertion works for specified signals, but I want to check all the signals in the design.
Can you give an example about how to check this situation ?

Thanks
 


Code Verilog - [expand]
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module a_test (
input [5:0] in_a,
input [3:0] in_b,
output c
 
); 
 
//psl    property as_eq_p = always ($size(in_a)==$size(in_b));
//psl    as_eq : assert as_eq_p;
 
assign c = ( in_a==in_b)? 1 : 0;
 
endmodule



you will need to compile with -psl
 

Using PSL for Verilog assertions is a bad idea in any situation. The SystemVerilog standard defines assertions as unified part of the language that does not need to be put in as comments.
 

you can use SVA, OVL, PSL - depends what tools you have.
you can also put the psl in a file instead of comment :

Code:
vunit check_length(tb.UUT)
{
    default clock = fell(Clk);

    property as_eq_p = always ($size(in_a)==$size(in_b));
    as_k : assert as_eq_p;

and compile with -psl my_psl_asertion_file.psl
 
Last edited:

Hi, guys,

Thank you. Now I know how to check this.

In modelsim, if I want to use system verilog assertion, just need to compile with -sv

Thanks
 

In modelsim, if I want to use system verilog assertion, just need to compile with -sv

Thanks
A better option would be to change the file extension to '*.sv'. If you use the -sv option, all of your Verilog files will be interpreted as SystemVerilog and that could be a problem if your Verilog code had keywords as identifiers now reserved in SystemVerilog.
 

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