Question about simulating noise of switched capacitor S/H

Hi,

I have a question about simulating the noise of a S/H circuit.

The method I am using right now is to simulate noise in sample and hold phase separately.

First, I put it in sample mode and simulate the noise over the sampling capacitor (CS) and hold capacitor (CH).

I used HSPICE .NOISE and integrated over entire frequency band. The result seems to match KT/C closely.

However, later I added a switch as noted in the diagram (represented by the red resistor Rp). If I use the noise voltage across capacitor + Rp, the noise is much higher. Rp contributes a lot of noise at higher frequency.

And I think I should use the noise voltage across the capacitor Cs only since it is the charge noise that we care.

Shall I include Rp in sample phase noise integration? Thanks!

I think you need to consider the noise voltage across Cs+Rp, since that is what manifests after amplification in hold phase as the noise at the output. In case of signal calculations, would you leave out Rp? Same applies to the noise as well. The introduction of Rp in series with the Cs will increase the bandwidth (introducing a zero in the transfer function, can be derived) which will increase the integrated noise voltage(noise increases also because of the noise by Rp itself).