Multi-phase detector in CDR circuit; Not half rate or full r

Dear all,

Recently I got a task to design a SerDes with around 1GHz data rate.
The tranmitter got a 100MHz local clock, and the the receiver got a similar but with a slight difference local clock, say 99.99MHz.

So I have to use a CDR in my receiver to extract the clock information from the embeded 8B/10B encoded serialized 1GHZ data stream.
SO my CDR will first use the local 99.99MHz as a clock reference, and I will need a Phase Dector to track the phase information of the serialized data stream.
Since I will use a CDR with multi-phase VCO, I am not sure the number of phases of that VCO, it could be 10 or 5.

I read a lot of papers, I didn't find any suitable phase detector for a 5 phase or 10 phases. I can see some papers with full rate or half rate phase detector from Razavi.

Anyone got relevant experience? Or should I generate a 1 GHz clock and use a full rate phase detector?

Thanks in advance,
Raymond

Re: Multi-phase detector in CDR circuit; Not half rate or fu

Are you saying that you want to switch phases for every bit-cell so that you can sample the data correctly? I don't know if it is going to work. You want to lock to the local oscillator which is off from the Tx one by some percentage. In this case in order to be able to sample in the right moment you will need more than 10 phases from the vco i.e. the granularity of the phase step should be sufficiently small to allow for correct adaptation of the sampling moment.

Re: Multi-phase detector in CDR circuit; Not half rate or fu

Dear sutapanaki

Thank you indeed. I 'd like to explain my system clear.

I have to build a 1GHz data rate SerDes in one chip. And I have a 100Mhz+/-100ppm local reference x'tal clock on this chip. Obviously, the 10:1 ratio is due to 8B/10B encoder on chip for DC balance.

TX structure.
8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> Serializer ==> 1 Bit @1GHz
I will use a PLL to generte the evenly spaced 10 phases of 100MHz clock which will serve the clock source for the serializer.

RX structure,
RX is receiving the 8B/10B coded data stream from another similar SerDes chip with embeded clock and slightly different frequency , say, 100MHz+/- 200ppm.
Since the local clock 100MHz+/-100ppm is different from in coming embeded clock, I will have to use a CDR to recover the clock from data with embeded clock.

1 bit @ 1GHz+/- 200ppm ==> CDR ==> 10 bit@ 100 Mhz +/- 200ppm PLUS 10 phases 100MHz +/- 200ppm

That's why I hope to have a sub-rate multi phase detector, say, 5 or 10 phase detector for the CDR.


If we use the quad-rate phase detector for CDR( there is a lot of from Razavi's students dealling with that) , I need to modify the SerDes entirely, especially at clock domain.

NEW TX structure
8 bit @ 100MHz ==> 8B/10B Encoder ==> 10 bit @ 100MHz ==> 10B/8B converter ==> 8 bit @ 125MHz==> Serializer ==> 1 Bit @1GHz

So will have to generate the 8 phases 125MHz from local reference clock.

NEW RX structure
1 bit @ 1GHz+/- 200ppm ==> CDR ==> 8 bit@ 125 Mhz +/- 200ppm PLUS 8 phases 125MHz +/- 200ppm ==> 8B/10B converter==> 10 bit@ 100 Mhz +/- 200ppm PLUS 1 phase 100MHz +/- 200ppm from addtional PLL.


It seems more work to me comparing with the previous structure, that 's why I am seeking the 5 or 10 phase sub-rate phase detector.

One more question, how about the frequency locking range of normal CDR phase detector, say 1%? Or less than 1 %?

Please advise,

Thanks in deed!
Raymond

Re: Multi-phase detector in CDR circuit; Not half rate or fu

Let me see if Your explanation was clear enough.
In TX you have 100Mhz which clocks the 8/10bit encoder i.e. 10 parallel bits of data are ready at the output of the encoder every 10ns. You need to serialize those 10 bits and transmit them serially. You can obviously put a MUX at the output of the 8/10 bit encoder and possibly use 10 phases of the 100MHz clock to pass through the data (although you'll need to disable the previous branch of the MUX and enable the next one).
At the RX side, you receive the data, which is 1Gbps raw serial data, which also appears at this point as if been clocked by 1 GHz clock (so this is the embeded clock) no matter what you did in the TX to transmit it. You want to produce 10 times smaller clock which is somehow locked to your 1Gbps data and have 10 phases of that clock to resample the data and put it in the 10/8 bit decoder.
Can you send me links to the works of Razavi's students that you mentioned?