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[SOLVED] How to write constrain for spi interface

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brainiac_rus

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Hello!

I want to write constraint for spi interface. FPGA is spartan-6 and i use ISE 14.7

______.png

Spi interface is the same as on picture. Clk line of SPI is the output of register.
I want to write constraints for this interface.

I tryed to write something:

Code:
NET "Data 1"     OFFSET = OUT 8 ns AFTER ClkIn REFERENCE_PIN "Clkout" RISING;
NET "CS"         OFFSET = OUT 8 ns AFTER ClkIn REFERENCE_PIN "Clkout" RISING;

But it does not work correctly, because program calculate delay between fpga input clock pad through pll or dcm and my values will not desirable

Code:
Timing constraint: COMP "d_dac_cs1" OFFSET = OUT 8 ns AFTER COMP "fpga_clkin0";
For more information, see Offset Out Analysis in the Timing Closure User Guide (UG612).
  1 path analyzed, 1 endpoint analyzed, 1 failing endpoint
  1 timing error detected.
  Minimum allowable offset is   8.047ns.
--------------------------------------------------------------------------------
  
Paths for end point d_dac_cs1 (W1.PAD), 1 path
--------------------------------------------------------------------------------
Slack (slowest paths):  -0.047ns (requirement - (clock arrival + clock path + data path + uncertainty))
   Source:               main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs (FF)
   Destination:          d_dac_cs1 (PAD)
   Source Clock:         clk_100MHz rising at 0.000ns
   Requirement:          8.000ns
   Data Path Delay:      6.755ns (Levels of Logic = 1)
   Clock Path Delay:     0.950ns (Levels of Logic = 4)
   Clock Uncertainty:    0.342ns
  
   Clock Uncertainty:          0.342ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.050ns
     Discrete Jitter (DJ):       0.238ns
     Phase Error (PE):           0.220ns
  
   Maximum Clock Path at Slow Process Corner: fpga_clkin0 to main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     D11.I                Tiopi                 1.557   fpga_clkin0
                                                        fpga_clkin0
                                                        clock_reset_module_inst/clock_manager0_inst/clkin1_buf
                                                        ProtoComp1070.IMUX.13
     BUFIO2_X4Y28.I       net (fanout=1)        3.012   clock_reset_module_inst/clock_manager0_inst/clkin1
     BUFIO2_X4Y28.DIVCLK  Tbufcko_DIVCLK        0.190   SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
                                                        SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
     PLL_ADV_X0Y3.CLKIN2  net (fanout=1)        0.885   clock_reset_module_inst/clock_manager0_inst/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
     PLL_ADV_X0Y3.CLKOUT4 Tpllcko_CLK          -7.330   clock_reset_module_inst/clock_manager0_inst/pll_base_inst/PLL_ADV
                                                        clock_reset_module_inst/clock_manager0_inst/pll_base_inst/PLL_ADV
     BUFGMUX_X2Y2.I0      net (fanout=1)        0.632   clock_reset_module_inst/clock_manager0_inst/clkout4
     BUFGMUX_X2Y2.O       Tgi0o                 0.209   clock_reset_module_inst/clock_manager0_inst/clkout5_buf
                                                        clock_reset_module_inst/clock_manager0_inst/clkout5_buf
     SLICE_X6Y27.CLK      net (fanout=49)       1.795   clk_100MHz
     -------------------------------------------------  ---------------------------
     Total                                      0.950ns (-5.374ns logic, 6.324ns route)
  
   Maximum Data Path at Slow Process Corner: main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs to d_dac_cs1
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X6Y27.AMUX     Tshcko                0.535   main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/state_reg_FSM_FFd1
                                                        main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs
     W1.O                 net (fanout=2)        3.878   d_dac_cs1_OBUF
     W1.PAD               Tioop                 2.342   d_dac_cs1
                                                        d_dac_cs1_OBUF
                                                        d_dac_cs1
     -------------------------------------------------  ---------------------------
     Total                                      6.755ns (2.877ns logic, 3.878ns route)
                                                        (42.6% logic, 57.4% route)
  
--------------------------------------------------------------------------------
  
Fastest Paths: COMP "d_dac_cs1" OFFSET = OUT 8 ns AFTER COMP "fpga_clkin0";
--------------------------------------------------------------------------------
  
Paths for end point d_dac_cs1 (W1.PAD), 1 path
--------------------------------------------------------------------------------
Delay (fastest paths):  3.876ns (clock arrival + clock path + data path - uncertainty)
   Source:               main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs (FF)
   Destination:          d_dac_cs1 (PAD)
   Source Clock:         clk_100MHz rising at 0.000ns
   Data Path Delay:      3.204ns (Levels of Logic = 1)
   Clock Path Delay:     1.014ns (Levels of Logic = 4)
   Clock Uncertainty:    0.342ns
  
   Clock Uncertainty:          0.342ns  ((TSJ^2 + DJ^2)^1/2) / 2 + PE
     Total System Jitter (TSJ):  0.050ns
     Discrete Jitter (DJ):       0.238ns
     Phase Error (PE):           0.220ns
  
   Minimum Clock Path at Fast Process Corner: fpga_clkin0 to main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     D11.I                Tiopi                 0.763   fpga_clkin0
                                                        fpga_clkin0
                                                        clock_reset_module_inst/clock_manager0_inst/clkin1_buf
                                                        ProtoComp1070.IMUX.13
     BUFIO2_X4Y28.I       net (fanout=1)        1.365   clock_reset_module_inst/clock_manager0_inst/clkin1
     BUFIO2_X4Y28.DIVCLK  Tbufcko_DIVCLK        0.122   SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
                                                        SP6_BUFIO2_INSERT_PLL1_ML_BUFIO2_0
     PLL_ADV_X0Y3.CLKIN2  net (fanout=1)        0.306   clock_reset_module_inst/clock_manager0_inst/pll_base_inst/PLL_ADV_ML_NEW_DIVCLK
     PLL_ADV_X0Y3.CLKOUT4 Tpllcko_CLK          -2.445   clock_reset_module_inst/clock_manager0_inst/pll_base_inst/PLL_ADV
                                                        clock_reset_module_inst/clock_manager0_inst/pll_base_inst/PLL_ADV
     BUFGMUX_X2Y2.I0      net (fanout=1)        0.190   clock_reset_module_inst/clock_manager0_inst/clkout4
     BUFGMUX_X2Y2.O       Tgi0o                 0.059   clock_reset_module_inst/clock_manager0_inst/clkout5_buf
                                                        clock_reset_module_inst/clock_manager0_inst/clkout5_buf
     SLICE_X6Y27.CLK      net (fanout=49)       0.654   clk_100MHz
     -------------------------------------------------  ---------------------------
     Total                                      1.014ns (-1.501ns logic, 2.515ns route)
  
   Minimum Data Path at Fast Process Corner: main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs to d_dac_cs1
     Location             Delay type         Delay(ns)  Physical Resource
                                                        Logical Resource(s)
     -------------------------------------------------  -------------------
     SLICE_X6Y27.AMUX     Tshcko                0.238   main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/state_reg_FSM_FFd1
                                                        main_0/adc_dac_calc_module_inst/dac_ad5542_ctrl_module_inst/spi_core_inst/cs
     W1.O                 net (fanout=2)        1.928   d_dac_cs1_OBUF
     W1.PAD               Tioop                 1.038   d_dac_cs1
                                                        d_dac_cs1_OBUF
                                                        d_dac_cs1
     -------------------------------------------------  ---------------------------
     Total                                      3.204ns (1.276ns logic, 1.928ns route)
                                                        (39.8% logic, 60.2% route)
  
--------------------------------------------------------------------------------

I have some questions about it

1) how to develop correctly spi core - clk output must be from register or from PLL/DCM/ODDR?
2) how to write correctly constrains for my case?
 

Considering maximum AD5542 clock frequency of 25 MHz, the pratical answer is: you usually get away without any IO constraints. If no large external delays are involves, e.g. slow drivers or opto isolators, you can rely on the standard SPI timing design, send data on one edge of the serial clock, latch it on the other edge. This gives sufficient margin to ignore any FPGA routing, I/O-cell or external wiring delay.

Presuming your design clock is faster than 25 MHz, generating the SPI clock by a register in the SPI interface is the preferred solution, because no second clock domain comes into play.
 
I use AD5542A - it has maximum SPI speed 50MHz
But in my design practice i get metastability on design with adc connected to fpga through isolator. And speed of that interface was 20 MHz, delay between clk on fpga net and miso net was about 26ns at worst case.
I need to do my design more reliable, besause it will be fly :)
 

External delays, e.g. of isolators will be usually considerably larger than FPGA delay and delay skew. Means a correct timing design is required in this case, but FPGA timing constraints and analysis are the lesser important part of it.

If possible, reducing the serial clock frequency is a simple way to achieve reliable timing. I don't know if you need to run the AD5542A at maximal speed.

If you still see a need to include the external SPI timing with your timing constraints, there are specific sections about describing IO delays in the respective manuals and tutorials, e.g. the Synopsys Timing Constraints user guide.
 

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