[SOLVED] what do 'set_max_delay' & 'set_min_delay' mean?

Hi all:
I saw the following descriptions for Setting Maximum and Minimum Path Delays:

pt_shell> set_max_delay 12 \
-from [get_cells REGA] -to [get_cells REGB]
With this timing exception, PrimeTime ignores the clock relationships. A path delay between
these registers that exceeds 12 time units minus the setup requirement of the endpoint
register is reported as a timing violation

pt_shell> set_min_delay 2.0 \
-from [get_cells REGA] -to [get_cells REGB]
Again, PrimeTime ignores the clock relationships. A path delay between these registers that
is less than 2 time units plus the hold requirement of the endpoint register is reported as a
timing violation

I think : 1) 12 is the max delay from CLOCK pin of REGA to DATA pin of REGB,
2)2.0 is the min delay from CLOCK pin of REGA to DATA pin of REGB

My question is why (12-setup time) not 12 is used to calculate setup timing violation and (2+hold time) not 2 is used to calculate hold timing violation?

Can anyboady help me.

Hi,

SETUP analysis:
The STA tool is used to ensure that the data arriving at the flop input is not arriving in the setup window.
In order to ensure it, the STA tool checks that (Arrival time) < (MAX_DELAY – Tsetup)

HOLD analysis:
The STA tool is used to ensure that the data arriving at the flop input is not arriving in the hold window.
In order to ensure it, the STA tool checks that (Arrival time) > (MIN_DELAY +Thold)

Consider the Violation Scenario example:
MAX_DELAY = 12
Arrival time = 11.97 (thus we meet the max delay constraint)
Arrival time of clock at the CK pin of FLOP = 12 (for example this is the first clock edge that comes after data arrival , this value cannot be less than 12, thus this is critical point value)
Setup time of flop = 0.18 (for example)


Thus we see that the time difference b/w clock arrival and data arrival is = 12 -11.97 = 0.03
But the setup time of flop is 0.18
Therefore we see that data is arriving in the setup window of flop. (which is a basic fundamental and is a violation)

We will never be able to catch this violation if we use “12” and NOT “12-setup” for checking setup violation.
Using 12-setup would flag a violation which we will have to FIX

Similar explanation goes for hold


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Shobhit

Hi shobhit:

Can I understand your explanation as follows:

1) SETUP analysis
Both data path and clock path can have a max delay(MAX_DELAY), but for correct samping reasons, data path must come earlier at least Tsetup time than clock path.

2) HOLD analysis
Both data path and clock path can have a min delay(MIN_DELAY), but for correct samping reasons, data path must come later at least Thold time than clock path.

Is my explanation right?

Max and min delays are only for the arrival times of Datapath.
It does not constrain the clock path

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Shobhit