Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

Error: Index <8> is out of range [0:7] for signal <ram>.

Status
Not open for further replies.
Q

QMA

Member level 4
Joined
Apr 5, 2007
Messages
72
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,286
Activity points
1,832
Dear all
I am trying a code in verilog with the following specs;
Code Verilog - [expand]
1
2
3
4
5
6
7
8
9
10
11
12

integer i;
reg [4:0]R_addr;
reg [7:0]temp;
reg [7:0] ram [0:7];
R_addr = R_addr - 1'b1;
for(i = 0; i<=R_addr; i = i+1)
begin
temp = ram[i];
------
------
------
end


I am getting the subjected error while synthesizing. Please tell me why i am getting the error and how can i overcome it.
 

For loops in Verilog should have compile time constants for iteration limits, otherwise the code isn't synthesizable. If R_addr isn't a constant then the code won't synthesize as that would represent run time self modifying hardware.

The reason the index 8 shows up is because reg [3:0] R_adder can hold a value of 4'd0-4'd15, which is obviously larger than the ram [0:7] unpacked index.
 
  • Like
Reactions: QMA

    Q

    QMA

    Points: 2
    Helpful Answer Positive Rating
if you just want to read from memory all you need is a mux


Code Verilog - [expand]
1

assign temp = ram[R_addr];
 
Last edited:

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top