preethi19
Full Member level 5
Hi all i am working on subthrshold region using pfet. I have done this before using nfet and using voltage source. I have good idea abt nfet where VGS < VTH and VDS can be neglected no matter wat the value is if its above VTH. But could anyone pls tell me how is it for pfet transistor. In nfet i used two voltage sources VGS and VDS and biased the transistor using VGS. Bulk was grounded.
But here my circuit is where( pfet) i have vdd (1V) which is connected to source and gate. Then a current source connected to drain and bulk. I am referring to a paper and its put the current is the biasing current and need to operate in subthreshold region. I am working in 180nm tech. so now i its totally different from what i did with nfet. I don't understand the bias current that too given in drain while vdd is given to VGS. Isn't VGS (ie vdd) responsible for biasing?? Also i don't understand the bulk part as to why they are giving the current source connection der too... I am in just beginning all this so little confusing. Can someone pls help...
But here my circuit is where( pfet) i have vdd (1V) which is connected to source and gate. Then a current source connected to drain and bulk. I am referring to a paper and its put the current is the biasing current and need to operate in subthreshold region. I am working in 180nm tech. so now i its totally different from what i did with nfet. I don't understand the bias current that too given in drain while vdd is given to VGS. Isn't VGS (ie vdd) responsible for biasing?? Also i don't understand the bulk part as to why they are giving the current source connection der too... I am in just beginning all this so little confusing. Can someone pls help...